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XIO2001: xio2001 Effect of not following startup sequence

Part Number: XIO2001

We are currently experiencing some intermittent issues with boards that contain the TI XIO2001 PCIe-to-PCI translation bus component. Earlier designs did not account for sequencing the GRST pin to start LOW and only transition to a HIGH state after voltage requirements (3.3V, 5V, VIO) have been met. We are implementing this sequence for new designs; however, what are the potential repercussions if this sequence is not followed? 
In our attempt to resolve existing issues, we believe this may be the explanation.
Thank you.
  • Hi Cameron,

    Could you please elaborate more on the issues you are seeing with the device, as well as the power sequencing you did before the fix?  We think the issues with the device could likely be caused by not following the sequence.

    Best regards,

    Greg

  • With our current design, GRST is always OPEN, therefore it is internally pulled HIGH as soon as 3.3V comes up. We are unable to 'see' the bridge and/or downstream devices. Our fix is to assert GRST to GND on startup and deassert the pin to HIGH as soon as 3.3V plane is up. We have not yet fabbed the solution on any new revisions but we believe this would solve our intermittent issue.

    Thank you.

    Cameron

  • Hi Cameron,

    Thanks for clarifying. If GRST# is being de-asserted before the 3.3V/1.5V is stable high, it can cause issues with the device's initialization and subsequent link training. 

    Best regards,

    Greg