DS125DF1610: Even with the same configuration applied to all retimer channels, certain channels have an unstable CDR lock or cannot lock.

Che-Jung Shih

Part Number: DS125DF1610

Hi Experts,

I am writing to seek advice regarding CDR locking issues we are experiencing on our load board.

We are following the same procedure that was successful on the EVM:
1. Set RX input to 550 MHz.
2. Configure VCO to 10.8 GHz with a /4 divider to target a 2.7 GHz PRBS7 signal.
3. Perform CDR reset for each channel.

While this works consistently on the EVM, the results on our load board are inconsistent: specifically, while some channels are stable, others fail to achieve CDR lock or experience frequent unlocks

.Are there any retimer registers or CTLE/DFE settings you suggest we adjust to compensate for potential board-level or channel-to-channel variations?

Any suggestion is will be appreciated.

5 months ago

0 Drew Miller1 5 months ago

TI__Mastermind 42748 points

Hi Che-Jung,

I have a few thoughts:

Is there flexibility in your input clock frequency? Typically we use a div-2/4/8/16 clock frequency relative to VCO setting. For 10.8 GHz, I'm wondering if you can try 675 MHz to see if this impacts your observations.
Do you observe any trends with CTLE / DFE settings between stable and unstable channels?
What amplitude is the clock?
Have you reviewed this FAQ? In particular, you may need to disable SBT check.
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/796045/faq-ds125df1610-how-to-setup-the-device-to-generate-different-prbs-pattern/2944514#2944514

Thanks,

Drew

0 Che-Jung Shih 5 months ago in reply to Drew Miller1

Prodigy 120 points

Hi Drew,

That at 675 MHz input, all channels can lock stably.
Our configuration uses a 675 MHz RX input, a 2.7 GHz VCO, and a 2.7 GHz retimer TX output. Right?

For the second question, we need to generate a 1.35 GHz clock (1010…). I attempted to write to registers 0x78 and 0x97, but the device did not accept the writes.

I also attempted the same configuration in SigCon, but the output waveform still does not exhibit the expected clock pattern.

SigCon:

Waveform:

Interface

Interface forum

DS125DF1610: Even with the same configuration applied to all retimer channels, certain channels have an unstable CDR lock or cannot lock.