• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 33 subscribers
  • Views 151 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS92LV2412: DS92LV2412 compatability mode for DS90C124

Eric Peterson61848
Prodigy 80 points

Part Number: DS92LV2412
Other Parts Discussed in Thread: DS92LV2411, DS90C124, DS90C241

Hello, the DS92LV241x ser/deser devices are 24 bit payload + 3 control bits for 27 bit total at up to 50Mhz which is 1.35Gbs. I need to shift 24 bits at 50Mhz clock (1.2Gbs) through a 1.25Gbs sfp. 

 

The DS90c devices are 24 bit but only accept a clock up to 35Mhz.

 

The DS92LV241x datasheet does not go into detail about the compatibility modes. If I run the DS92LV241x devices in compatability mode for the DS90C devices (24 bit, no control bits), does this mean that the DS92LV241x devices ignore the 3 control bits and only send the 24 bit payload?

 

Can i run a DS92LV2412/DS92LV2411 pair in DS90C compatability mode to form a 24 bit stream at 50Mhz for 1.2Gbs? 

 

Thank you,

Eric

  • 0
    Prodigy 80 points

    Correction: After more digging, i found the DS90C "frame" also has control bits and will also exceed the speed of the sfp i am using. Back to the drawing board.

  • 0 in reply to Eric Peterson61848
    TI__Mastermind 18530 points

    Hi Eric,

    Thanks for the question. Just want to clarify that the compatibility mode would be like so - a DS92LV211 serializer paired with a DS90C124 deserializer for example, or a DS90C241 serializer paired with a DS92LV2412. The compatible devices are listed here (sorry, there is a typo on the Table 10). 

    Can you explain what the sfp is and what your intended use case is (display specifications, soc output, etc)? Happy to help you find the proper solution for your use case. 

    BR,

    Esther

  • 0 in reply to Esther Chang
    Prodigy 80 points

    The SFP is a 1.25GBs optical module. That is setting the max bit rate. The use case is a 24 bit raw parallel bus to serial -> optical -> serial to 24 bit raw parallel bus.

    The goal was to send a 24 bit payload over fiber at a bit rate <=1.25GBs. Part of the payload is MII data that needs to be clocked at a multiple of 25Mhz.

    I currently have the link working using DS90Cx devices at 25Mhz but that only generates a bit rate of ~600MBs and is wasting a lot of potential of the 1.25GBs optical transceivers. Since the clock needs to be a multiple of 25MHz, I wanted to go to 50Mhz. The DS90Cx ser/deser are only good to 35MHz so I was hoping to switch to the DS92LV241x ser/deser. However, including control bits, the total frame is 28 bits and that makes the bit rate 1.4GBs. Too fast for the optical module.

    I misread the DS90Cx datasheet and mistakenly thought the total frame was 24 bits. Therefore, I was hoping that "DS90Cx Compatibility Mode" of the DS92LV241x ignored the 3 control bits and the total frame was 24 bits.

    But, none of that is correct because the DS90Cx devices also have control bits added to the 24 bit payload so my current working link actually has a bit rate of ~700MBs.

    In the end, what I want to do is not possible with the DS90Cx or the DS92LV241x devices. The DS90Cx will not do 50Mhz and the DS92LV241x exceeds the max bit rate at 50MHz.

    I have decided to use a Lattice FPGA with built in ser/deser so I can define the parallel bus width. That way I can run at 50MHz and adjust the parallel bus width to maximize the 1.25GBs fiber transceiver. That is not possible with a fixed parallel bus width of 24 bits (+ control bits).

    Thank you

  • 0 in reply to Eric Peterson61848
    TI__Mastermind 18530 points

    Hi Eric,

    Thank you for the detailed explanation. Please do not hesitate to reach out again if you need any assistance with finding any TI parts for your use cases in the future.

    BR,

    Esther