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DP83867IS: Linkup issue

ttd
Mastermind 9115 points

Part Number: DP83867IS

Dear Technical Support Team,

 

DP83867IS connected to Zynq(PS-MIO) via RGMII and it has linkup issue.

Could you advice me to acheive linkup?

 

The DP83867IS determines its startup behavior based on strap settings which configured as follows:

RX_D2: Pulled down with 1 k ohm

RX_D0: Pulled down with 1 k ohm

RX_CTRL: Set to Mode 3 using a resistor divider

INT/PWDN: Pulled up with 2.2 k ohm

 

VDDIO is supplied externally at 1.8 V.Since this is a two‑supply configuration, VDDA1P8 is open.

 

 

Configuring Ethernet Devices With 4-Level Straps (Rev. A)

DP83867 Troubleshooting Guide (Rev. C)

www.ti.com/.../slvrbn1

Best Regards,

ttd

  • 0
    TI__Mastermind 26771 points

    Hi, 

    Could you share the schematic so we can check the HW connections? Also, can you verify that the PHY is alive? Could you check PWDN, RST_N are high and XI pin is getting 25 MHz clock? Is the PHY powering up according to the power ramp requirements?

    Best,
    J

  • 0 in reply to J
    Mastermind 9115 points

    Hi J,

    I can achieve linkup, it is due to cable connection issue.

    Thank you for your support.

    I have another question.

    Regarding the RGMII specifications for the DP83867IS,
    is it LVCMOS? Or is it HSTL?
    Currently, VDDIO is set to +1.8V, so looking at VIH/VIL and VOH/VOL, it appears equivalent to LVCMOS.

    Output Levels
    　VOH 1.6V or higher
        VOL 0.2V or less

    Input Levels (VIH/VIL)
     VIH 1.26V or higher
     VIL 0.36V or lower

    In the FPGA, I selected LVCMOS 1.8V and connected it via RGMII. 

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 26771 points

    Hi ttd, 

    RGMII on DP83867 uses LVCMOS. 

    Best,
    J