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DP83867IR: There are certain issues with the DP83867IRRGZ Ethernet PHY chip.

ian wu
Expert 1065 points

Part Number: DP83867IR

hi  expert

1. The network port using the DP83867IRRGZ chip exhibited transmission errors, resulting in packet loss on the lower-level device.
2. Through hardware measurement of the FPGA TXC and TXCTL signals, the following phenomena were observed:
(1) When the TXC clock phase is 2ns ahead of the TXCTL, no packet loss occurs. The waveform diagram measured by the oscilloscope is as follows.

1.png

 

2.jpg(2) When the TXC clock is aligned with the TXCL, a large number of packet losses occur. The waveform graph measured by the oscilloscope is as follows

 

3.jpg

3. The FPGA sends data to the PHY chip. The internal delay within the TX is configured as 2ns. Theoretically, sending along the same edge is correct. This issue needs to be confirmed with you (the Strap resistors of LED1 and LED2 are in the "not connected" state).

4.png

Could you please clarify this for us? Specifically, which sequence should we follow when adjusting the RGMII transmitter? And why is the second approach not feasible?

  • 0
    TI__Mastermind 44955 points

    Hello,

    I would want to readjust the way this is being looked. Any data needs to have enough settling time prior and post clock rising edge, called setup and hold time. On the assumption that PHY is not adding extra internal delay (done in step 3), first scope image shows 4ns of setup time, which is plenty sufficient. Looking at the second image, clock and data are aligned, but issues are seen. Theoretically, with an extra clock delay on an aligned signal, this should be working fine. Changing strapping on would be difference between 2ns or 0ns skew between clock and data. Is the signals probe as close to receiver as possible?

    Sincerely,

    Gerome