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DP83867IR: DP83867 Config and Hardstrap Issue

David Lin
Prodigy 10 points

Part Number: DP83867IR

We are observing an issue related to the RX_CTRL hardstrap pin (configured using external 5.76 k ohm pull-up and 2.49 k ohm pull-down resistors as a voltage divider). This issue does not occur 100%, and some boards do not exhibit the problem.

On affected boards, the IC enters a failure state and does not operate correctly. Even when we assert the reset signal, the divided voltage on the RX_CTRL pin remains incorrect.

The only way to recover the device is to perform the following steps:

Remove the external pull-up and pull-down resistors on the RX_CTRL pin.

Measure the RX_CTRL pin to ground using a multimeter in resistance (ohm) mode. The measured resistance initially reads a few k ohm, then gradually increases, eventually rising to approximately 50–60 k ohm.

Reinstall the pull-up and pull-down resistors. After this, the IC resumes normal operation.

This behavior suggests that the multimeter's resistance measurement (which applies a small voltage or current) clears an internal fault condition inside the IC.

We also observed that even after the issue has been resolved, the failure may reoccur if the board is left unused for an extended period of time.

Do you have any insights or recommendations that could help us resolve this issue?

  • 0
    TI__Mastermind 42585 points

    Hello,

    Are you conducting impedance measurements on a live circuit? I would not recommend this approach. 

    Most strapping issues step from poor timing and external circuitry affecting the bias point set by the resistors. To rule out this hypothesis, I would like to suggest the following experiment:

    - Sever connection between PHY and SoC via series resistor depop or cut trace. 

    - Turn on PHY, and hold in reset via pin. Measure voltage at pin while in this state.

    - Measure across a handful of boards and power cycles to rule out elusive behavior.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 10 points

    Hi Gerome,

    Thank you for your reply.

    All resistance measurements were performed while the board was powered off.
    What we observed was that the measured impedance initially appeared to be a few kohm, then gradually increased over time, eventually reaching around 50–60 kohm. This behavior seemed unusual to us, and it led us to suspect that the measurement itself might be clearing or resetting an internal condition in either the FPGA or the PHY.

    Next, I will scope the timing of VDD, XI, RESET_N, MDC, and RX_CTRL.
    I will also try keeping the ETH RESET signal asserted until the FPGA hardware I/O configuration is completed, and then de-assert it to see if this resolves the issue.

    Sincerely,
    David

  • 0 in reply to David Lin
    TI__Mastermind 42585 points

    Hi David,

    It is pretty weird that there is some power-off latching behavior occuring. Is this happening with all units? I know its sporadic, but I am curious about the sample size. Looking forward to your plots.

    Note: I am OoO thru end of week.

    Sincerely,

    Gerome