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SN65DSI84-Q1: REFCLK related issues confirmed

Alan Xia
Genius 11140 points

Part Number: SN65DSI84-Q1

Hi team,

Please help clarify the following questions regarding the SN65DSI84-Q1 REFCLK:

1. What percentage of rise time and fall time are required?

2. What is the input capacitance of the SN65DSI84-Q1 REFCLK pin?

3. The rise time/fall time requirement of 0.1ns-1ns considers an input frequency range of 25MHz-154MHz. If a 25MHz OSC is used as the REFCLK input, can the rise time/fall time requirements be relaxed, and if so, by how much?

  • 0
    TI__Mastermind 29020 points

    Hi Alan,

    To answer your questions,

    1. The rise and fall time specifications are for 10% to 90%.

    Also mentioned in this thread: SN65DSI83: The rise and fall times of REFCLK for SN65DSI83

    2. This is not currently shared in the datasheet. Is this specification required to choose a device?

    3. According to this specification, requires the rise/fall time spec to be met for 25 MHz REFCLK input as well.


    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Genius 11140 points

    Hi Ikram,

    1. Where is 10% to 90% from?

    In some OSC datasheet, the output tR/tF  are 20% to 80%. Below data is from the draft datasheet of CDC6Cx-Q1 shared by TI team before.

    tr/tF   Output Rise/Fall Time  20% to 80% of VOH-VOL, CL = 15 pF, normal mode    0.57(TYP)-2.2ns(MAX)

    2.CL is a key input for the OSC. Please share the capacitance value of the SN65DSI84-Q1 REFCLK pin.

  • 0 in reply to Alan Xia
    TI__Mastermind 29020 points

    Hi Alan,

    I referred to the previous E2E thread for the 10-90% rise time value.
    If the oscillator chosen has max rise time at 2.2ns for 20-80%, then it is already not meeting this specification and it would be worse for 10-90%. Is there any alternative parts you are looking at?

    Another option may be to use the DSI clock as the LVDS clock source. If the DSI clock lane meets the SI requirements for DSI and the clock specifications shown in the datasheet, then the customer could also consider just using the DSI clock as the source.

    I will check the value for input capacitance for REFCLK and get back to you.

    Best regards,
    Ikram

  • 0 in reply to Alan Xia
    TI__Mastermind 29020 points

    Hi Alan,

    I referred to the previous E2E thread for the 10-90% rise time value.
    If the oscillator chosen has max rise time at 2.2ns for 20-80%, then it is already not meeting this specification and it would be worse for 10-90%. Is there any alternative parts you are looking at?

    Another option may be to use the DSI clock as the LVDS clock source. If the DSI clock lane meets the SI requirements for DSI and the clock specifications shown in the datasheet, then the customer could also consider just using the DSI clock as the source.

    I will check the value for input capacitance for REFCLK and get back to you.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Genius 11140 points

    Hi Ikram，

    Thanks，looking forward to your reply.

  • 0 in reply to Alan Xia
    TI__Mastermind 29020 points

    Hi Alan,

    I could not find a specification for input capacitance. The REFCLK input used should be with an oscillator which are self-oscillating, so the input capacitance will not be critical. The EVM for example, uses a CDCEL913PW for REFCLK.

    Input capacitance is more critical for crystals, but the DSI84 REFCLK should use an oscillator, not crystal.

    Best regards,
    Ikram