Part Number: DP83867CS
- Is it appropriate to select Channel A for general use?
- Are there any specific differences between selecting Channel A, B, C, or D for the clock output?
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Part Number: DP83867CS
Hi Waki-san,
DP83867 does not support PHY side timestamping according to IEEE 1588. This PHY can only do Start of Frame Detect for IEEE 1588 Time Stamp. What type of PTP are you trying to implement? Could you explain what type of PTP you are trying to implement so we can best support on configuration?
I believe that by configuring the CLK_O_SEL register to "receive clock", I can output the recovery clock from the CLK_OUT pin. Is this understanding correct?
Your understanding is correct.
Is it appropriate to select Channel A for general use?
Channel A should be good to use for recovered clock.
Are there any specific differences between selecting Channel A, B, C, or D for the clock output?
The only difference is that you would be selecting recovered clock from different channel since each channel would have 125MHz clock, but there may be slight differences in phase in each channel's recovered clock.
Best,
J