AM2432: AM2432 PCIe-to-GPMC Bridge: Unexpected Extra FPGA Accesses

Greetings,

Can you share what software base you are using? Is it Linux, the MCU+SDK, or some custom code specific for your use-case?

Sincerely,

Lucas

We are implementing it on a custom board based on the Industrial Communications SDK for AM243x – RTOS Version: 2025.00.00.08.

Thank you for the information, this will help me find the right resource for this. I have some minor follow up questions as well about the addressing, can you share the details on:

• What GPMC address ranges (or rather FPGA address range) is the host accessing in the AM2432 when you specifically see this issue? 
• How have you mapped the address ranges in the PCIe BAR setup? 
• Does this issue occur at specific addresses or does it occur for any arbitrary address tried?

Sincerely,

Lucas

What GPMC address ranges (or rather FPGA address range) is the host accessing in the AM2432 when you specifically see this issue?
＞0x50000000~.　

How have you mapped the address ranges in the PCIe BAR setup?
> Sorry, I'm not the software engineer, so I don't know the details, but I can share the PCIe settings from sysconfig.
If more details are needed, I'll ask the software team.

PCIe Instance : PCIE 0
Operational Mode : EP mode
Operation Speed : Gen2
Number of Lanes : 1
Reference Clock Mode : External Reference Clock, no SSC
SRIS Configuration : Disable
Legacy Interrupt Pin : Pin none
Number of MSI Vectors : 1
Inbound Address Translation
Region Index : 1
Transaction Layer Packet Type : Memory Type TLP
Lower Base Address : 0x4000
Upper Base Address : 0x0
Lower Target Address : 0x50000000
Upper Target Address : 0x0
Region Window Size : 0x0
BAR Aperture : 16KB
Bar Configuration : 32bit Mem BAR Non Prefetchable

Does this issue occur at specific addresses or does it occur for any arbitrary address tried?
> In our system, the host currently only accesses 0x50001014. When accessing 0x50001014, the addresses transition over 4 cycles as 1010, 1012, 1014, 1016, with WE asserting at the 1014 timing.
This behavior does not occur during GPMC's standalone write access to the FPGA.

Hello ,

When the Host writes 4 bytes via PCIe to address 0x50001014 (GPMC region), the AM2432 generates 4 GPMC cycles with addresses cycling through 0x1010, 0x1012, 0x1014, 0x1016. The WE signal is asserted only during the cycle at address 0x1014.

I feel the observed behavior is caused by internal bus width expansion in the AM2432 interconnect.

The PCIe write transaction passes through the following path:

PCI → Internal Interconnect → GPMC Controller → External Bus

The internal interconnect aligns transactions to 64-bit (8-byte) boundaries. When a 4-byte write targets address 0x50001014:

1. The interconnect aligns to the 8-byte boundary: 0x50001010
2. An 8-byte transaction is generated with byte-enables indicating only the valid bytes (at 0x1014)
3. GPMC controller converts the 8-byte transaction to four 16-bit bus cycles
4. WE is asserted only for the cycle containing valid data (0x1014)

To confirm this root cause, please perform the following test:

Test 1: Different Write Sizes from Host :

│ Host Write Size: 2 bytes │ Expected GPMC Cycles: 4 cycles │ Expected WE Assertions:  1 WE 

│ Host Write Size: 4 bytes │  Expected GPMC Cycles: 4 cycles │Expected WE Assertions:  2 WE 

│ Host Write Size: 8 bytes │ Expected GPMC Cycles:4 cycles │ Expected WE Assertions: 4 WE 

Please share the above test results ..

Regards,

Anil.