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TDP2004: Some qusetions and schematic review

Jeff YANG
Mastermind 8715 points

Part Number: TDP2004

Hi,

Our design utilizes 2 DisplayPorts (DP), with each DP using only 2 lanes. Can these 4 channels be divided into 2 independent groups (2 lanes per group)?

  1. Can these two groups be enabled or disabled independently?

  2. Can these two groups be configured with different Equalization (EQ) settings?

Please help review the circuit/schematic.

And below comment from AI, would you please help check is it correct?

"MODE = L2 is the smartest choice, especially for your unique 'one-to-two' split application. The SMBus/I2C Secondary Mode (L2) of this chip provides the highest level of flexibility. In your specific use case, maintaining L2 offers several key advantages:"

Why is L2 the most beneficial for your design?

  • Independent Channel Fine-tuning: Only in I2C mode can you perform independent Equalization (EQ) compensation and Flat Gain settings for each individual path (Channel 0-3). This is critical for handling two sets of DP traces with different lengths.

  • Dynamic Power Management: You can use software commands to power down the unused Link B (Ch2, 3) at any time to save energy—a level of control that is impossible in Pin-strap mode (L0).

  • 0
    Mastermind 8715 points

    Hi,

    Here is the schematic. Thanks!

  • +1 in reply to Jeff YANG
    TI__Guru**** 187071 points

    Jeff

    On the schematic review

    1. Please make sure both input and output main link are AC coupled with 0.22uF, size 201 capacitors

    2. Please make sure the I2C bus has pullup resistors on them

    ***

    The AI response is correct as you can enable/disable channel, and change EQ on the fly.

    1. Can these two groups be enabled or disabled independently?

    2. Can these two groups be configured with different Equalization (EQ) settings?

    Yes, in I2C secondary mode, channel register base address 0x00 -> Channel 0, 0x20 -> Channel 1, 0x40 -> Channel 2, 0x60 -> Channel 3. 

    For channel enable or disable, this is done through register 0x05

    For EQ configuration, this is then done through register 0x01 and 0x03

    Below is the example of TDP2004 I2C configuration

    <aardvark>
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/>
    <i2c_bitrate khz="100"/>

    ======Disable TI Test Mode======
    <i2c_write addr="0x18" count="1" radix="16">84 04</i2c_write>/>

    ======Enable TDP2004======
    <i2c_write addr="0x18" count="1" radix="16">05 FF</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">25 FF</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">45 FF</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">65 FF</i2c_write>/>

    ======Set EQ======
    <i2c_write addr="0x18" count="1" radix="16">01 52</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">21 52</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">41 52</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">61 52</i2c_write>/>

    ======Set Gain======
    <i2c_write addr="0x18" count="1" radix="16">03 7D</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">23 7D</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">43 7D</i2c_write>/>
    <i2c_write addr="0x18" count="1" radix="16">63 7D</i2c_write>/>
    </aardvark>

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Mastermind 8715 points

    Hi David,

    thank you, I will let you know if any other questions. Thanks!

    Jeff