TMDS181: TMDS181 sometimes doesn't work at startup

Hi Amano-san, 

TMDS clock at 4K60 resolution is supposed to give 594MHz clock so the yellow signal is normal. Is the input white signal and the output yellow signal? It seems like the white input is actually looking weird for 4K60 input. 

And does TMDS181 registers become not accessible when you input HDMI 2.0 resolutions as an input?

Could you measure VDD, VCC, and OE when the device gets into this state? If this is happening on multiple boards, I wonder if the device is not getting enough power. 

Best,
J

J,

Since the datasheet specifies max. 340 MHz, so wouldn't it be unexpected to operate it at 594MHz?

(The dot clock for 4K60 is 594 MHz, but isn’t the TMDS clock supposed to be 148.5 MHz?)

Under normal operation, the input and output TMDS clocks should be 148.5 MHz.

-Yellow signal: Output TMDS clock

-White signal: Input TMDS clock

In this case, TMDS181 registers cannot be accessed even with HDMI1.4.

If we can reproduce the problem, I'll check VDD, VCC, and OE.

Thank you and best regards,

Nagi

Hi Amano-san, 

I was mistaken. You are correct that the TMDS clock lane should output 148.5MHz clock in 4K60. 

A couple of comments on the schematic:
1. HPD_SRC is not connected. Does the source have HPD connection?
2. Please ensure OE is coming up after the power is fully up. Based on the current schematic, I am unsure if the OE pin is going up after the power is fully ramped up. What is the time difference? Please refer to the power up requirement diagram below:

3. I noticed that DDC buffer is connected to both SNK and SRC pins. Is the DDC buffer connected to the source and the sink? Also, for DDC snoop feature, you have to connect to the DDC_SNK pins. 

Best,
J

J,

1. Yes, Source HPD is connected to Sink HPD and HPD-SNK.

2. I checked Power-up sequence, it is no problem. (See attached image, Yellow: VCC/Blue: VDD/Red: OE)

There is a spike on OE, but it is below 0.8V, so it is within the specified.

3. No, DDC snoop is connected to only DDC-SNK.

R1218/1219 are not populated, so DDC-SRC is connected to GND.

Thank you and best regards,

Nagi

Hi Amano-san,

The spike could cause an issue since it goes for VCC for a second. Could you try and see if the issue is resolved when you assert OE pin low and then high?

Best,

J

J,

Thanks for your advice.

However, reproducibility is very poor.

And we are currently repeating the reproducibility tests.

Is it correct that the same symptom occurs if OE is set to High before Power-up sequence?

If so, I'll check with OE set to High before Power-up sequence.

Thank you and best regards,

Nagi

Hi Amano-san, 

The same symptom can occur if the OE is set to high before the power-up. Could you try removing U1204 and ensure C1217 is 0.1uF to see if passive RC circuit fixes the issue? TMDS181 has internal pullup so the OE pin will naturally rise high with the RC circuit. 

Best,
J

J,

Since the problem was reproduced in the automated testing, I checked the following:

-VDD, VCC, and OE are no problem.

-The problem was recovered after OE was set to Low, then to High, and input signal was removed and reinserted.

-Intentionally, OE set to High before Power-up sequence, the frequency of occurrence has increased. (3/378 times)

-Removed U1204, and added 0.1uF, the frequency of occurrence has decreased. (0/2683 times)

It seems like the problem is close to being resolved, but I still don't understand the root cause.

I checked Power-up sequence after removing U1204 and adding 0.1uF. (See attached image, Yellow: VCC/Blue: VDD/Red: OE)

I would appreciate the following questions:

1. OE doesn't meet td2, but is this unrelated if OE isn't controlled?

2. Power-up sequence appears the same as U1204, but is something changing internally? (OE rises simultaneously with 3.3V and before 1.2V.)

Thank you and best regards,

Nagi

Hi Amano-san,

1. We recommend to use larger capacitor to ensure that the ramp time for OE pin is slower and meets the datasheet requirements.

2. It may be possible that the device’s digital block was backpowered from the OE pin had the blip and put the device into a bad state. We have never characterized device for those kinds of situation so we cannot be sure however.

Best,

J

J,

Thanks for your reply, and I made a mistake.

The above board may have been damaged during automated testing.

I checked Power-up sequence after removing U1204 and adding 0.1uF on a different board. (See attached image, Yellow: VCC/Blue: VDD/Red: OE)

I will try automated testing on a different board.

I would appreciate the following questions:

-OE is around 2.4V, is it no problem?

Thank you and best regards,

Nagi

Hi Amano-san, 

Are you still seeing display when OE pin is 2.4V? The datasheet does specify that 2.6V is the minimum for VIH of OE pin. However, this value is when the microcontroller drove logic high/low. When the RC circuit is used to drive the OE pin, we expect that the OE pin may not rise above 2.6V but the device will still function properly. 

Best,
J

J.

I found the following similar questions:

-TMDS181: Internal Threshold for OE Pin When Using Capacitor - Interface forum - Interface - TI E2E support forums

td2 is too long with 0.1uF, so I'd like to consider a smaller value.

Therefore, I'd like to know how to measure td2. (90% of VCC 3.3V -> 90% of OE 2.4V?)

Thank you and best regards,

Nagi

Hi Amano-san, 

Yes, your understanding is correct on the below measurement setup.

Nagi Amano said:

Therefore, I'd like to know how to measure td2. (90% of VCC 3.3V -> 90% of OE 2.4V?)

Best,
J