DP83867E: SI test failed

Hi Rannie,

This looks very marginal. Is customer seeing any functional issues and if not, is it an acceptable pathway to move forward?

Looking at their schematic, their transformer is out of spec on the RL from 80-100MHz and this could contribute to their reported behaviors.

Sincerely,

Gerome

Hi Gerome,

No, it's unacceptable.

Gerome Cacho said:

Looking at their schematic, their transformer is out of spec on the RL from 80-100MHz and this could contribute to their reported behaviors.

I noticed that the BW of GST5009MLF is 100MHz. Can you help to recommend a suitable transformer here?

BTW, I noticed that the transformer in customer board has similar spec of the transformer in our EVM.

Is there any register to modify this?

BRs,

Rannie

Hi Rannie,

I would like to take a look at layout first to ensure there are not any suboptimalities that are contributing to the design. Can you please provide either Altium file or .PDF of every layer with each page for single layer?

Sincerely,

Gerome

Hi Gerome,

Please find below issue summary:

My customer Advantech reported DP83867 failures in MDI Peak Output Voltage testing (1000Base-T).

Key observations:

• Customer tested 3 boards, 2 chips each. 3 chips failed and all 3 boards has failed IC —some at U79, some at U82.
• All the IC has the same marking as below figure.
• The failed item is Point C or Point D output voltage mismatch. (the test report can be seen in attachment Failed.zip)
• Swap the failed IC, issue follows DP83867.
• The 4pcs Intel(I266) PHY on the same board has no issue.
• Attachment is the layout, sch and test report.

Support need:

1. Is this a known device-to-device variation? Could it be related to manufacturing lot, calibration, or specific register settings? 
2. Any further debugging steps to help customer identify the root cause? Please advise on next steps.

Attachment: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/83867.7z

IC marking: 

register: (Both 2 ICs (good one and bad one) has the same register)

//0x19 0x4004 

//0x18 0x6B10 

//0x1A 0x03 

Below register are written to avoid the short cable (<1m) unstable link issue.

BRs,

Rannie

Hi Rannie,

Allow me until end of week to process the layout.

Sincerely,

Gerome

Hi Rannie,

A few items noticed:

- Ensure that all MDI traces have a reference GND underneath. Appears that some secondary traces on the transformer have no ground reference and are floating

- Secondary of transformer has no bob-smith termination

- Secondaries of CT of transformer are connected together. We do not recommend this

- Ensure clocking is following good PPM requirement

- Is ESD diodes populated? These may add increased capacitance

Sincerely,
Gerome

Hi Gerome,

Thanks for the detailed layout checklist. I’ve shared it with the customer, but I’d like to highlight a key observation from their side that may shift the root cause focus.
The customer did a cross‑validation:
· They swapped the “fail” chip to a known good board → still fail
· They swapped a “pass” chip to the original board → still pass
This strongly suggests the issue follows the specific device, not the PCB layout or surrounding components. The failure is consistent across boards with the same layout.
Given this, I’m wondering:
1. Could this be related to device‑to‑device variation (e.g., internal calibration, trimming, or process spread)?
2. Is there any known issue with certain date codes or lots regarding MDI output levels?
3. Should we request the customer to return the fail devices for FA (failure analysis)?
The customer is waiting for a clearer conclusion. Your help to dig into the chip‑level root cause would be greatly appreciated.

BRs,

Rannie

Hi Rannie,

It appears from the reports you have provided, while peaks a, b, and d are within spec, there seems to be a mismatch on where peak c should be. The 1G spec is really really tight. To help your customer, I do have a register which can help. Can you look to decrease the value of Reg 0xA3[12:8] while setting [13] = '1' from the default position? This can help with peak C performance with the device.

Sincerely,

Gerome

HI Gerome,

Can you help to confirm 0xA3[13] and [8:12] is for peak D or peak C?

BRs,

Rannie

Hi Rannie,

Gerome is currently out of office.

However, the bits you mentioned are for channel D. I am not quite caught up with the history here but is the customer failing the peak C for channel D? A2/A3 registers are meant to be tuned for the failing channel. A2 register is for channel A and B and A3 register is for channel C and D. Please advise the customer to tune the register according to Gerome’s suggestion based on the failing channel.

Best,

J

Hi J and Gerome,

Update my customer test results after modifying the register.

Setting the register of A3[12:8] to 00000 and below is the test results, still not pass, moreover, the point A&B which was passed previously was failed after modifying the register.

Do you have further debugged method?

BRs,

Rannie

Hi team,

Is there any update?

BRs,

Rannie

Hi Rannie,

I apologize for the delay in response. A2/A3 can be tuned to 32 different values. Could they try 2F instead of all 0s? 

Best,
J

Hi J,

The customer has tried tuning register 0xA3[12:8] to both '00000' and '2F' as suggested. Unfortunately, the test results for Point C are still failing. Furthermore, the customer noted a concerning trend: the signal quality becomes worse when the register value is increased. Additionally, modifying this register for Channel C also negatively impacted the previously passing Point A and Point B results. 

BRs,

Rannie

Hi Rannie,

Is it possible for customer to provide the compliance results when tuning in either direction? Our methodology would be to tune this register in a certain direction to see how the compliance test results are impacted. Our understanding is that by decreasing default value for appropriate channel in Reg 0xA2 or 0xA3, this can optimize for passing results in the right direction.

What channel/MDI pair is being tested? Customer should tune only this value accordingly.

Sincerely,

Gerome

Hi Gerome,

Customer test also shown that decreasing the value will optimize the results but even decrease to 0, it can't be optimized to "pass".

Default: Channel D:

Decrease to 0: (improved but still over spec, also, the point A and B are out of spec)

BRs,

Rannie

Hi Rannie,

I am bringing this issue to my design team attention. Please expect a response in a few days.

Sincerely,
Gerome

Hi Rannie,

I am still awaiting input from my design team. Please expect next response by Tuesday.

Sincerely,

Gerome

Hi Rannie,

My design team is occupied by some existing activities. I will update EoD Thursday.

Sincerely,
Gerome

Hi Gerome,

Thanks. Looking forward to your reply.

BRs,

Rannie

Thank you for your response.

Hi Rannie,

As an update, my design team is still looking into this. 

In the meanwhile, has customer replaced the units with new samples to see if new units are also showing this issue?

Also as a heads up, I will be on TBK thru Tuesday. My internal team is still queued for this and I hope to provide their feedback upon my return.

Sincerely,

Gerome

Hi Gerome,

Update the test with new samples. Customer test 2pcs new D/C samples and found the performance was improved. The worst case is 2.05% (2% pass) compared previous 2.71% and 2.38%.

The support needs:

1. Whether this issue is known?
2. Help to identify the D/C that has issues.
3. Help to provide the root cause. Which electrical performance impact the DP83867 behavior?

BRs,

Rannie

Rannie

Is this the same issue as being discussed in the email?

Thanks

David

Hi David,

Yes, we are discussing through email.

BRs,

Rannie

Hi Rannie,

Lets continue discussion over email.

Sincerely,

Gerome