Part Number: SN65DPHY440SS
Hi team,
TI.com provides S-parameter models (.s4p) instead of traditional IBIS or IBIS-AMI models.
- As an active device (Retimer), we typically expect an IBIS-AMI model for SerDes-type simulations to account for non-linear behavior and clock recovery.
- S-parameters are generally considered passive models. How can we perform a reliable system-level Signal Integrity (SI) simulation (e.g., in ADS, Sigrity, or HyperLynx) using only S-parameters for an active retimer?
- Does this model accurately reflect the internal gain, equalization, and redriving characteristics, or is there a hidden/separate model available for active simulation?
The datasheet only lists EQ gain values for specific frequency points: 500MHz and 750MHz.
- Does TI have a complete EQ frequency response curve showing the gain across the entire spectrum?
- Specifically, what is the expected EQ gain at lower frequencies, such as 250MHz (500Mbps)? We need this data to evaluate signal over-equalization risks.
Based on the datasheet, the maximum EQ gain at 750MHz (1.5Gbps) is 5dB. According to the MIPI specification, the allowable insertion loss at this frequency is 2dB.
- Is it correct to assume the total supported link insertion loss is approximately 5dB (EQ) + 2dB (Spec) = 7dB?
- Can we use this 7dB value as a hard constraint for our total PCB trace and connector loss budget? If not, what is the recommended methodology for calculating the maximum channel loss this chip can compensate for?