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DS320PR822: DS320PR822 – PCIe x4 link downgraded to x2 when used as redriver/mux

Part Number: DS320PR822

Hello,

I am using two DS320PR822 devices as redriver/mux in a PCIe design.

System architecture:

  • 1 PCIe controller
  • 2 possible PCIe endpoint devices
  • PCIe x4 interface
  • Two DS320PR822: one for the TX path (controller → device) and one for the RX path (device → controller)

The redrivers are used to route the PCIe lanes to one of the two endpoints. 

Issue:
When checking with the lspci command, the PCIe device is detected as x2 instead of x4.

To isolate the issue, I removed the redrivers and directly connected the inputs to the outputs with wires. In this configuration, the link correctly trains to x4, suggesting the issue is related to the DS320PR822.

Configuration:

The devices are used in pin-strap mode (1kR pull-down on MODE pin)

  • PD0 and PD1 tied to GND (device enabled)
  • SEL0 and SEL1 tied to GND (controller connected to device 1)
  • EQ and gain set to default values

RX detection:
I tested the following modes:

  • “Outputs polls until 3 consecutive valid detections” with an 8.25 kR pull-down
  • “Tx polls every 150 µs until valid termination is detected” with RX_DET floating

The issue remains the same in both cases.

Could you advise on possible causes for losing two lanes in this configuration or any recommended settings for a PCIe x4 application?

  • Hi Maxime,

    Does the link-up reach gen5 (or endpoint's maximum advertised speed)? 

    Strap settings look OK. Could you send a schematic so I can check connections to the devices? 

    Best,

    Charles 

  • Hi Charles,

    The endpoint device is currently limited to PCIe Gen3 x4. In the current configuration the link successfully reaches Gen3 speed, but it trains only as x2 instead of x4.

    Here an extract from the schematic:

     

    Best Regards,

    Maxime

  • Hi Maxime,

    Please see my comments: 

    1. EQ and gain are strapped as expected. 
    2. Since MODE and RX_DET pins are shared between both DS320PR822s, please use resistor values that are half the values listed in table 7-4 (e.g. L0:500Ω to GND, L1: 4.125 KΩ to GND).  Please use 500Ω resistor for R0521 (MODE pin) and 4.125 kΩ resistor for R0522 (RX_DET resistor).  
    3. When the link trains as x2, which two lanes (out of 4 lanes) link up? Is it the same lanes each time? 

    Thanks,
    Charles

  • Hi Charles,

    I tried the solution you suggested of dividing the values by two because of the two devices on pins MODE and RX_DET, and it's now working as expected.

    LnkSta: Speed 8GT/s (downgraded), Width x4 (downgraded)

    Thanks for your support!

    Maxime