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TUSB7320: TI.TUSB7320 possible PCIe communication via adjust Payload dismatching condition

Neil Chen
Prodigy 120 points

Part Number: TUSB7320

Hi Sirs, 

Current, I have an one project (also sharing part diagram as picture), this one shows use PCIe Switch/PI7C2G608 then connect to TI.TUSB7320 for reach "PCIe to USB bridge" implementation case.  

image.png After bring-up testing, we found this design route will cause system hang-on "0x 71" (Port-80) message and cannot boot into shell/O.S successfully. 

We contacted to PCIe Sw vender (Diodes.PI7C2G608) this issue topic, they found possible "payload dismatching during PCIe interface initial communication process" cause then try to adjust PCIe Sw relative Payload setting, although can get small improvement (0x 71 => 0x 92) but still not boot into shell successfully. 

image.png

Now, we test remove PCIe Sw <=> TUSB7320 AC-Caps (PCIe TX/RX lane) route and see system can boot into shell/O.S successfully for power on-off testing over 3000-times. Therefore, we would like to asking does TI have meet similar issue before? 

Or, do you have any debug analyze idea at this moment? (e.g. PCIe Switch <=> TUSB7320 design route)

Plz help to brain-storming and wait for your response, many tks!

BRs

By Neil

  • 0
    TI__Guru**** 162331 points

    HI Neil:

      TUSB7320 payload is 1k Byte , how about  the payload of ASM1456 ?

      Can you remove ASM1456 and just keep TUSB7320 and test again?

      How about the fail rate for power cycle test?

    Regards

    Brian

  • 0 in reply to Brian Zhou
    Prodigy 120 points

    Hi Brain, 

      (1) TUSB7320 payload is 1k Byte , how about  the payload of ASM1456 ?

    => For ASM1456 chip, I will asking the corresponding vender to confirm. 

    => if we want to try adjust payload size of TUSB7320, how we can make it? (should using external EEPROM) 

    => How about the default payload size setting of TI.TUB7320? 

      (2) Can you remove ASM1456 and just keep TUSB7320 and test again?

    => Sure, we can arrange other schedule to try it. 

      (3) How about the fail rate for power cycle test?

    => Base on the current testing result, the fail rate is 2% (twices losing in 100-times cycle). 

    BRs

    By Neil

  • 0 in reply to Neil Chen
    Prodigy 120 points

    Hi Brain, 

    the ASM1456 is a high-speed HSIO mux/de-mux chip implement, so this one isn't necessary consider extra payload size issue. 

    that's why remove PCIe SW <=> TUSB7320 AC-CAPs actual reason. 

    So, the TUSB7320 payload can support maximum 1K Bye after review datasheet mentioned, have a couple question to asking : 

    (1) if we want to adjust payload size of TUSB7320, how to make it? (e.g. should using external EEPROM) 

    (2) what is the default payload size definition? 

    Welcome if you have any go futrher on next, and waiting for your update. 

    BRs 

    By Neil

  • 0 in reply to Neil Chen
    TI__Guru**** 162331 points

    Hi Neil:

          TUSB7320 payload is fixed inside . But you may able to change  payload  from PI7C2G608 though RW  or other PCIe tool in PCI configuration .

    Regards

    Brian