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TIC10024-Q1: TIC10024QDCPRQ1 comparator detection time vs Maxim's input deglitch

Jose Maroto
Expert 3795 points

Part Number: TIC10024-Q1

Dear team,

Could you please provide feedback to questions below? Thanks:

"

We have some doubts about the contact monitor, let me give you some background before jumping to the questions.

We were using the CM from Maxim (MAX20091ATM) in the past, with which we were having misreading input issues at low temperatures (-40deg). Studying the route cause, we realize that Maxim CM has a “deglitching” strategy that is a time delay to filter possible glitches that all CM inputs have. This delay plus the one that input capacitance adds to total reading time may compromise the correct open switch reading at polling mode (the only current that charge the external capacitance is the wetting current).

 

With that said, we want to understand what is the maximum delay that TIC10024QDCPRQ1 has at its inputs at worst case conditions. From datasheet, we only see “comparator detection time” with nominal value = 18us.

 

The questions are:

  • What is exactly the “comparator detection time”?
  • Is there any “deglitching” strategy at CM inputs?
  • What is the maximum delay time that the CM adds to the total reading time under worst case conditions? I am referring to the maximum delay time from when the input voltage level reaches the programmed threshold until this event is reported.

"

Rgds, Jose

  • 0
    TI__Mastermind 35820 points

    Hello Jose,

    See my answers below:

    1. The "comparator detection time" is the time it takes the inputs to be sampled.

    Each input will take 18us (typical) to sample and have its switch status stored in the IN_STAT_COMP register. Once the last input is stored, the part will start from IN0 and start the sequence again. This sequence is determined by Poll_Time. 

    2. From my knowledge there are no "deglitching" filters on the inputs.

    Regards,

    Josh

  • 0
    TI__Mastermind 35820 points

    Hello Jose,

    Sorry, I didn't answer customer's third question.

    3. As I mentioned in my first response, inputs are only sampled within the T_Comp window. If, for example, the input voltage level reaches the programmed threshold but the T_comp window has already passed, the customer would need to wait until the input is sampled again which will be determined by your Poll_Time

    Regards,

    Josh

  • 0
    Prodigy 30 points

    Hello Josh,

    Thank you for the clarification. Let me check if I'm getting correctly what you are saying. 

    As an example, in our design we have a Low Side Switch connected to CM ground switch monitor input (from IN10 to IN23). The input has connected 47 Ohm series resistor and a 47nF capacitor. When the low side input transition occurs (from close to open), the only current that is charging the 47nf capacitor is the wetting current coming from the CM (in polling mode).

    The input configuration is as follows:

    1) Polling time = 64ms

    2) Polling active time = 128us

    According to your clarification, to be able to catch every time a correct input reading, we have to be sure that the programmed threshold is reached within t_comp window (typ 18us), otherwise we are not going to catch the "open switch" state. In other words, the time that takes to charge the input external capacitor to reach the programmed threshold must be less than 18us, otherwise, we are not going to read an open switch. Is this statement correct? 

  • 0 in reply to Claus Nosetto
    TI__Mastermind 35820 points

    Hello Claus,

    It is correct the tComp window is used to sample the input but let me correct myself on a couple of things. 

    When we look at tPoll_Time, tPoll_Act_Time and tComp, the actual timing operation is described as follows:

    1) During tPoll_Act_Time, the current sources or sinks are enabled to bias the external switch. Wetting currents are on for the configured time (128us) to give enough time to charge up any external capacitors which may be in use.

    2) Shortly before tPoll_Act_Time is over, the comparator samples the voltage on the INx pin. During this time, tPoll_Act_Time is still high and the current sources/sinks are still active

    3) After tPoll_Act_Time is over, the sample phase of the comparator is complete, and the current source is turned off

    4) The comparator then converts the data to the digital output when tPoll_Act_Time is over.

    To catch a change in input state, the event needs to happen within the tComp window. However, tComp occurs towards the end of the wetting current timeframe.

    Regards,

    Josh

  • 0 in reply to Joshua Salinas
    Prodigy 30 points

    Hello Josh,

    Now it is clear and aligns with our tests.

    I think that the polling mode time sequence graph in datasheet is not that clear in terms of when the tComp window is taken:

    In fact, the tComp window taken at IN23 occurs after the polling active time window. It is as if you could set 'when' the comparator window occurs (beginning, end or after polling active time) could it be? or is it always taken, as you already explained, at the last 18us of polling active time? 

    Speaking about tComp_typ=18us, could you also share the maximum tComp_max value?

    Thanks for the clarifications.

    Regards,

    Claus Nosetto

  • 0 in reply to Claus Nosetto
    TI__Mastermind 35820 points

    Hello Claus,

    Yes I agree the timing diagram needs to be clearer where the TIC10024-Q1 truly samples the inputs.

    Let me ask our design team this question and the tComp min/max values. Thanks!

    Regards,

    Josh

  • 0 in reply to Joshua Salinas
    Prodigy 30 points

    Hello Josh,

    Are there any updates about tComp min/max values? Thanks!

    Regards,

    Claus Nosetto

  • 0 in reply to Claus Nosetto
    TI__Mastermind 35820 points

    Hello Claus,

    I was able to confirm the tComp is measured towards the end of the tPoll_Act_Time. See graph below

    However, the team only captured typical data for tComp and not min/max values. 

    Regards,

    Josh