SN65DSI83-Q1: Display panel flickering with sn65dsi83 + external clock source

Hi Vojtech,

The timings set from the DSI source SoC should match the panel timings. Are the resolution and timings set from the SoC exactly matching the active and blanking periods and clock rates? 

Please check whether the datasheet initialization sequence is followed. The init sequence has requirements for power-up, setting enable, register configs, and DSI clock and data lane states. Please ensure that the DSI clock source is always in HS state.

When the issue occurs, does the flickering happen during run-time, randomly while system is running, or does it occur after power-up and continue flickering?

Best regards,
Ikram

Hello Ikram,

We used the resolution, timings and clock rate defined by the panel but the issues still occured. The current timings configuration is a result of our testing.

The initialization sequence is done as described in the datasheet. We will measure the DSI clock source to make sure it is in HS state.

The flickering always happens right from power up and continues while the system is running.

When the external refclk is used the issue occurs on every boot. When the DSI clock is used then it happens in about 2 % of restarts and it can be fixed or caused by toggling the PLL_EN bit (reg 0x0D).

Thanks for reply,
Vojtech

Hi Vojtech,

Since the issue is happening after power-up and initialization, it's likely related to the init. sequence. 

Please make sure that the DSI clock is always in HS state, and data lanes are in LP11 at the start, then changed to HS state as shown in the init sequence. Also note the resets and delays required.



The REFCLK causing flickering could be related to a mismatch between the pixel clock rates of the DSI not matching the rate of the REFCLK. When setting these, please make sure the REFCLK multiplier, or DSI clock divider are set accordingly to meet the LVDS clock frequency. You can refer to this resolution guide for this: [FAQ] SN65DSI84: SN65DSI83, SN65DSI84, and SN65DSI85 resolution guide

Best regards,
Ikram

Hello Ikram,

I will go over the initialization sequence again and measure the DSI clock lanes. 

As for the REFCLK, we use 3 DSI lanes, the DSI clock is running at 300 mhz, this divided by 4 gives us 75mhz which is also our targeted lvds frequency as our panel supports 70 - 76.6 mhz.

Thanks
Vojtech

Thank you Vojtech, please let us know if there are any further questions or updates for this setup.

Best regards,
Ikram

Hello Ikram,

As far as we can tell we follow the initialization sequence for the chip correctly.
We have also measured the Enable, DSI clock and one DSI data lane (N + P) during boot that resulted in a flickering screen (which turned black within 5 seconds). 

This looks identicall to boot sequence which results in working display.

Apart from trying to measure all DSI data lanes at once we are not sure how to progress with this further.

Thanks,
Vojtech.

Hi Vojtech,

It looks like the DSI clock is not in HS state. There should be continuous clocking on the DSI clock input. Here we only see a pulse before EN is set.

The DSI clock should be in HS state and data lanes should be in LP state before EN is set. 

An example of the waveforms is shared here: [FAQ] SN65DSI84: No display output with SN65DSI83, SN65DSI84, SN65DSI85

Best regards,
Ikram

Hi Ikram,

The device used to measure the signals did not display the DSI CLOCK properly, see the following picture captured with another device:

The DSI CLOCK and DSI DATA are brought to 0 for about 800 ms before the events on the picture, before that the DSI data is in LP11 and DSI DATA is in HS mode. This is different from the picture you shared. However when the enable is brought up the DSI CLOCK and DSI DATA should be in a correct state.

Thanks,
Vojtech.

Hi Vojtech, please give me 1-2 days to look further into this issue.

Hi Vojtech,

If test pattern with both external reference clock and DSI clock shows no issue, then there is likely an issue either with

• DSI data lanes: such as SI issue, DSI packet not being in the correct states, or timing mismatch
• Initialization sequence issue: delays and resets not being set as shown in datasheet

In the initialization sequence you will notice that DSI data lanes are switched from LP11 to HS state, with DSI stream started AFTER the register initialization and resets. Please check whether this is followed.



Best regards,
Ikram

Hello Vojtech and  Ikram, 

Interestingly, we are facing the same issue. The specs of our system are:

- 1280 x 800 LVDS panel @ 72 MHz
- SN65DSI83-Q1 converter IC (4 data lanes + clock lane)
- Qualcomm-based SOC, kernel 4.19

We are using a clock derived from the MIPI D-PHY and are seeing an approximately 25% failure rate.

The issue manifests as a flickering screen in about 1–5% of power-on cycles. It never appeared after the boot (during operation).

This is strangely familiar to your issue. I am confident that we are correctly following the initialization sequence and that the PCB layout is correct.

After so much time spent debugging the issue, we will probably be looking for an alternative panel with an MIPI interface. 

If (or better to say when) you find the solution, please write it here. 

Best regards, 

Miha

Hi Miha, 

From our understanding the DSI clock or REFCLK is likely not causing the issue if test pattern is always working. The issue it could be related to the DSI data timings or steps in initialization such as the the PLL and soft resets. There are delays, and then afterwards the DSI data lanes are set to output and DSI data being sent in HS mode could cause an issue during startup.

Additionally, there may issues with DSI data input skew or similar hardware/layout concerns. The SoC can also be checked by changing the DSI modes, and whether issue follows a particular DSI non-burst or burst mode, with or without sync pulses. 

Another test could be to use the video restart sequence shared in the datasheet and checking if the issue clears after restarting.

Please let us know whether the restart sequence or changing the DSI modes resolved the issue.

Best regards,
Ikram

Hello Ikram,

I will check the highlighted points.

Thanks.

Hi Vojtech, thank you. Let us know when there are new findings.

Best regards,
Ikram