TPS3435-Q1: Review TPS3435CAKAGDDFRQ1 circuit

Hi Vinyas,

Is there a pullup resistor on the WDO net? This is an open drain active low output that requires a pullup resistor and voltage.

Can you confirm my understanding of the circuit is the desired configuration:

• The WD-EN pin is enabled when the logic level is high and disabled when logic level low. As it is now the watchdog is disabled via R12044 (47kohm) to ground unless a signal is provided on IGN_INT or WD_EN_FROM_VIP.
• I assume either the top or bottom resistor on SET0 and SET1 will be depopulated. As it is now with all resistors populated SET0 and SET1 are at 0.5*VDD which is a gray area for the logic level.
  

Thanks,
Joshua

Hi Joshua,

Joshua Garcia said:

Is there a pullup resistor on the WDO net? This is an open drain active low output that requires a pullup resistor and voltage.

Yes we have an 10k Pullup to P_5V_KA on the other page of schematic.

Joshua Garcia said:

The WD-EN pin is enabled when the logic level is high and disabled when logic level low. As it is now the watchdog is disabled via R12044 (47kohm) to ground unless a signal is provided on IGN_INT or WD_EN_FROM_VIP.

Yes only when IGN_INT or WD_EN_FROM_VIP are triggered the Watchdog is enabled

Joshua Garcia said:

I assume either the top or bottom resistor on SET0 and SET1 will be depopulated. As it is now with all resistors populated SET0 and SET1 are at 0.5*VDD which is a gray area for the logic level.

Yes , we will depop the top resistors 

ONE MORE QUERY:

We have the WDI PWM coming from microcontroller in 3V3 power domain. So we were planning to change the circuit as below so to meet the WDI requirement of VIH as minimum 0.7VDD.Do you see any risk as the WDI is edge triggered?