Part Number: DP83867IR
Dear support team
In the past, we prioritized placing the PHY as close as possible to the MAC (MCU or FPGA) to minimize trace length on the MII interface. This design strategy was based on the assumption that single-ended - in our case 3.3V DDR (Double Data Rate) MII signals - are more susceptible to signal integrity issues than the differential MDI signal pairs.
Now we have read the application report from Lysny Woodahl "Ethernet PHY PCB Design Layout Checklist " that recommends the opposite: Ethernet PHY PCB Design Layout Checklist

My question: What is the rationale behind the 2-inch maximum trace length requirement for MDI (Medium Dependent Interface) traces between the PHY and magnetics? This constraint seems particularly strict given that:
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The cable on the other side of the magnetics can be up to 100 meters long
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The 1:1 transformer ratio means the magnetics don't fundamentally alter the signal characteristics
What makes the pre-magnetics interface so critical compared to the post-magnetics cable?