This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB635-Q1: How to verify the Back channel input jitter (tJIT-BC) of serializer

Part Number: DS90UB635-Q1

Hi,

How can we verify the back channel input jitter of serializer of MPN:- DS90UB635-Q1.

Please provide the process step by step.

 

Thanks& Regards,

Manoj Kumar

  • Hi Manoj,

    I am currently looking into this and I will get back to you by the end of the week, 3/27. 

    Thank you for your patience,

    Ethan Woods

  • Hi Manoj,

    Do you have a local FAE that could be looped in here on this?

    This testing procedure is under NDA restrictions, so it is not possible to share the process/documentation here. If you have a local FAE you can contact, we can share the information with them in the internal forums on a new post or through a private email chain.

    If not, I can try to put a high-level overview of the process together that I can share here, but I cannot share the full details and process.

    Best regards,

    Ethan Woods

  • Hi Ethan,

    Yes, we have local FAE. But right now, you can share the high level overview, if any issue occurs then we contact through FAE for full details and process.

    Thanks &Regards 

    Manoj Kumar

  • Hi Manoj,

    After communication with the rest of the team, we have come to the conclusion that this testing procedure is outdated and could be validated much easier by testing/verifying that the channel specifications in the system are met. We also do not recommend/expect customers to directly test back channel rx jitter tolerance on the serializer. By ensuring that IL/RL is met in the system, it is inherently validating the back channel jitter as well. Since the back channel TX driver characteristics are known, validating the channel specifications means that the back channel jitter requirements are met. 

    In addition, you would need to meet other deserializer specifications which relate to the back channel TX, such as power noise and REFCLK jitter. By meeting these specs, then the output jitter will be low on the backchannel transmitter and within the expected value. These are expected values to meet during design, so the real test would mainly be passing channel spec.

    Since channel specification test procedures and details are also under NDA, please have your local FAE reach out to request access to the documents through the following site:

    https://sps16.itg.ti.com/sites/HSDCOVERVIEW/EFL/FPD-Link/_layouts/15/start.aspx#/SitePages/Channel%20Specifications.aspx

    Thank you for your understanding,

    Ethan Woods

  • Manoj,

    If you still want the testing process for verifying back channel input jitter, I can draft a testing procedure as stated above in a high level or give the method to the FAE. We do not typically expect customers to test back channel rx jitter tolerance, since this is something that we have just done in validation.

    Best regards,

    Ethan Woods