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AM2434: Two Ported EtherNet Interfacing Using TS3DDR3812 and DP83869's

Thomas Jones
Prodigy 10 points

Part Number: AM2434
Other Parts Discussed in Thread: TS3DDR3812, DP83869

Good Morning

I am current working on a design using the AM243x (the ALX package), a TS3DDR3812 mux, and a pair of  DP83869's to the EtherNet Phy Layer components.  We are planning to use two EtherNet ports so the RGMII1/2 along with the CPSW..etc come into play.  

  1. Are the signals for the MDC and MDIO connected directly between the two DP83869's or must they go from the AM243x pins through a mosfet switcher to each DP83869 separately?  One app note said one way, the other said the other way.  Or is this switcher internal to the SoC?
  2. The software team is currently using the LP-AM243x Launchpad eval board.  They want to have the EtherNet connections to the same ports on the AM243x on our design as the eval board.  I have found the interface to the TS3DDR3812 mux in the Launchpad manual.  However, in page 36 (Figure 4-10) it shows the RGMII1/2...etc signals to the mux, and then it references Items 11 and 12 (goes to the SoC).  I am unable to find these references to I can verify my connection to the SoC against what they are using on the Eval board.  Please assist.
  3. Also, as a side question, does TI have an option on using one external crystal for the SoC and the two DP83869's through a CDCLC1310 crystal mux or will that cause timing issues?

Thank you for your time.

 

  • 0
    TI__Guru 64335 points

    The Ethernet management interface, signals MDC and MDIO, was defined to operate as a multi-drop bus by IEEE many years ago. It allows a single interface to manage multiple Ethernet PHYs. Therefore, the multi-drop connectivity found in the AM243x LaunchPadTm Development Kit is a valid connection topology. Where did you find an application note that says you should switch these signals between devices?

    AM243x has two of these interfaces. One is associated with the PRU_ICSSG and the other is associated with CPSW. The AM243x LaunchPad is using the one associated with CPSW (pins W1 and V2) shown on page 12 of the schematic. The AM243x LaunchPad schematic has a mistake, where the MDC and MDIO signals and AM243x pins W1 and V2 have the wrong signal function name. They should not have the "PRG1_" prefix. The interface associated with PRU_ICSSG (pins D2 and E4) are shown on page 11 of the schematic, where they are used for GPIO signal functions.

    The TS3DDR3812 mux was only used on the AM243x LaunchPad to allow the Ethernet PHY (U19) associated with RGMII1 to be connected to PRU_ICSSG or CPSW.  The mux was not needed for the Ethernet PHY (U7) associated with RGMII2 because the RGMII2 signals from PRU_ICSSG and CPSW share the same AM243x pins. That is not the case for the RGMII1 signals, so the mux was needed to select connectivity to the PRU_ICSSG RGMII1 signals or the CPSW RGMII1 signals. I would not expect your system to need the mux. You would simply connect the Ethernet PHY to the appropriate AM243x pins based on your expected use case.

    One potential problem with connecting a single crystal to a CDCLC1310 and having it drive all three devices is IO voltage compatibility. The AM243x device only allows a 1.8V signal for its reference clock input and the Ethernet PHYs are operating at 3.3V. You would need to check if the Ethernet PHYs are able to use a 1.8V reference clock when operating at 3.3V.

    Regards,
    Paul