Part Number: TSB12LV32-EP
Other Parts Discussed in Thread: TSB41BA3A-EP, TSB12LV32
Hello,
We have a legacy product which has used the TSB12LV32-EP (LLC) and TSB41BA3A-EP (PHY) combination successfully for a number of years. Due to processor obsolescence we have had to replace our main microcontroller with a new variant. This device does not have a parallel port interface so we are simulating the parallel port by driving GPIO pins in the correct sequence.
The TSB12LV32-EP is configured with a BCLK at 8MHz and is configured in handshake mode using burst read\write to transfer the data. Generally the device is working as expected with no issues. However, we are seeing intermittent data loss with this configuration. During our investigation we have noted that inserting some additional delays following a quadlet read or write improves the situation significantly (no data loss after a long soak period). We also found that reducing the BCLK frequency to 4MHz improved the situation with regard to data loss (but does not allow us to meet timing requirements).
In order to help us resolve the problem we were hoping you could answer the following questions:
1. Handshake mode timing margins at 8MHz BCLK:
- Are there undocumented internal timing constraints specific to handshake mode (at 8MHz)?
- Is there a minimum recovery time between consecutive handshake transactions beyond "wait for next BCLK rising edge"?
- Could 225-387.5ns inter-transaction gaps be too fast for internal state machine settling at 8MHz?
2. ATF FIFO burst write timing:
- Are there special timing considerations for burst writes to the ATF FIFO in handshake mode?
- Could rapid consecutive writes (64 quadlets in ~15-25µs) cause cumulative timing stress?
- Is there a maximum recommended write rate for ATF FIFO in handshake mode?
3. BCLK frequency recommendations:
- What is the maximum recommended BCLK frequency for reliable handshake mode operation?
- Are there known reduced timing margins at 8MHz vs 4MHz?
- Is 8MHz considered within normal operating range for handshake mode?
4. **Inter-transaction timing sensitivity:**
- Does the TSB12LV32 require variable timing between transactions, or is fixed-pattern timing acceptable?
- Could executing many transactions with consistent 225-325ns gaps create timing accumulation issues?
Please let me know if you need any additional information.
Scope plot of handshake interaction.
