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SN65DSI83Q1-EVM: Can't get the pll to lock.

Gerald Coleman
Prodigy 60 points

Part Number: SN65DSI83Q1-EVM

All I want to do is to get the test pattern to show up on our LVDS display.  I've generated many CSR register files - and none of them will get the PLL to lock.  I'm trying to use the internal 27Mhz REFCLK with a 2x multiply, then enable the PLL.  And it still won't lock.  I can never see the LVDS clock do anything.  Is there some sort of magic set of CSR values that will just get the clock to run?  If I can't get a clock - I don't see how anything else will work.

  • 0
    TI__Mastermind 32030 points

    Hi Gerald,

    On the EVM there is an LVDS REFCLK, please probe and check whether the 27 MHz signal is received at the DSI83 REFCLK pin. This will help to confirm that any rework or soldering is not needed to connect the on board REFCLK to the DSI83.

    To generate the CSR values, are you using the DSI Tuner tool? Please use the DSI Tuner GUI to generate the initialization settings and make sure the entire datasheet "Initialization Sequence" steps are followed. Also, please check whether test pattern mode is enabled (there is also checkbox on the GUI to enable this). The display timings set on the device should be the same as what the display datasheet specifies.

    If you are using the DSI Tuner, you could also share your entries screenshots here so we can check whether other changes are required.


    Best regards,
    Ikram