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DP83826I: Clearification LED behavioral

Thomas Donner
Prodigy 170 points

Part Number: DP83826I

We did a new design with the DP83826I and had some struggels with the LEDs and there abilities.
PHY is in enhanced mode (MII).

None of the LED(0-3) Pins has default an Link output by default (LEDCFG), right?
The only cfg_ledX_gpio_ctrl who is not writeable ist cfg_led3_gpio_ctrl, right?
The Configuration of the Link signal in Register LEDCR (0x18) of an PHY internatl Signal who can be mapped to on of the 3 cfg_ledX_gpio_ctrl (Not LED3), right?
MLED is the synonyme of LED0, right?
What excaltly does MLEDCR Bit 9?
With Register LEDCFG2 the logic of LED-Pin 1, Led-Pin2 can be inverted or a fixed value can be given out, right?

There are several register related to LED who are type R/W but undokumented and from type "Reserved" (LEDCFG Bit 3-0, LEDCR Bit 0, MLEDCR Bit 15-10 & 8-7, ...), thats confusing.


What we need is a pin who reacts as a Link for EtherCat by default. 
It look like there is none who did this by defaut, right.


  • 0
    TI__Guru**** 188601 points

    Hi,

    I would point you toward this app note. When setting up the PHY to work in an EtherCAT® system, it is important that the PHY has an LED which is set up to show 100 Mbit full Duplex and the signal polarity is active low or configurable for some ESCs. Below is the configuration example for LED1.

    LED 1 Write to PHY register 0x460 value 0x0005 (100Mbit speed)

    Write to PHY register 0x469 value 0x0004 (Active High polarity)

    Write to PHY register 0x304 value 0x0008 (Set pin 31 function to LED1)

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Prodigy 170 points

    This is not an EtherCat only design.
    We have although support other protokolls.


    Write to PHY register 0x304 value 0x0008 (Set pin 31 function to LED1)
    -> this is the Default value of this Register. No change needed


    Let me resume: by default none of the LED Pins has usabe signal for EtherCat IP (0x0 or 0x5 or 0xA) by default.
    Every Pin need a reconfiguration. Correct?

    Kind Regards
    Thomas Donner

  • 0 in reply to Thomas Donner
    TI__Guru**** 188601 points

    Thomas

    In DP83826 Enhanced Mode, RX_ER needs to be strapped high to enable LED1 function on Pin 31. Once the LED1 function is enabled, the LED is ON when link is 100Mbps, meets the EtherCat requirement.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 170 points

    Hi David

    A first fast test validate what you are saying. 
    But Im a littel bit confused because the datasheet says:


    This Pin is a 10 MBit signal by default and i read back a value of 0x6 in this register (LEDCFR).

    But her is described something other:



    Kind Regards

    Thomas Donner

  • +1 in reply to Thomas Donner
    TI__Guru**** 188601 points

    Thomas

    This is a typo in the LEDCFG register (0x460) which we will correct in the next revision of our datasheet.

    Bit [3:0] are the LED1 control as shown below.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 170 points

    Because I searched this kind of Signal I switched over to LED3.
    But LED3 has in MII Mode another behavioral than decribed in 0x460. So we had to cut two PCB Tracks and make a bridge between two testpoints.

    Uncorrect datasheets costs the customers time and PCB Designs.

    I think a flow chart for the LEDx outputs would be helpful.

    Kind Regards

    Thomas 

  • 0 in reply to Thomas Donner
    TI__Guru**** 188601 points

    Thomas

    There is a high level block diagram for the LED and GPIO configuration in the DP83826 datasheet as shown below. But I will keep your feedback in mind on making the LED functional description and configuration easier to understand.

    Thanks

    David