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TLK2501: Application issue.

Reed
Expert 2170 points

Part Number: TLK2501

Hi Team,

Attached are the schematic diagram and PCB board. Please help review them
In addition, there are the following questions currently, please help answer them:
1. Is there a problem with the TLK2501 running 1080P 60HZ at full frame rate at 2.5G.
2. Is there a problem using a 150MHZ crystal oscillator for TLK2501.
3. Is there a problem using the 2.5G TLK2501 in a 3G optical module.
4. For the TLK2501 50R external component, is there a need to optimize the circuit.
5. Confirmation of technical support strength and methods.
6. Provide a software demo for TLK2501 on the FPGA side.

SCH_MAG-DMAL-V120260318_6-P06_FPGA_SERDES_2026-03-25 (2).png

PCB_MAG-DMAL-V1202603018_2026-03-25.pdf 

  • 0
    TI__Intellectual 2076 points

    Hi Reed,

    I will have a response by end of day Thursday.

    Best,

    Charles 

  • 0 in reply to Charles Wang
    Expert 2170 points

    Charles,

    Looking forward to your reply, thank you!

  • 0 in reply to Reed
    TI__Intellectual 2076 points

    Hi Reed,

    I will need some more time to check in with my team. I will have my response by end of day Monday. Sorry for the delays.

    Best,

    Charles

  • 0 in reply to Charles Wang
    Expert 2170 points

    Hi Charles,

    Any update?

  • 0 in reply to Reed
    TI__Intellectual 2076 points

    Hi Reed,

    Here are my comments for schematic review: 

    1. R482 should not be 0 ohms. RREF is recommended to be 200 ohms for 50 ohm impedance traces.  
    2. Biasing for the TLK2501's high speed side looks OK.
    3. Please double check your SFP module vendor 's recommended circuit for biasing. Usually the SFP module will have biasing and termination resistors built in.  
    Reed said:
    1. Is there a problem with the TLK2501 running 1080P 60HZ at full frame rate at 2.5G.

    I'm not familiar with 1080P 60Hz full frame's raw data rate. Due to 8b/10b encoding on the serial interface side, maximum raw data rate for TLK2501 is 2Gbps. Additionally, please ensure provisions are made to drive TX_EN/TX_ER to send IDLEs for initial link-up. 

    Reed said:
    2. Is there a problem using a 150MHZ crystal oscillator for TLK2501.

    150MHz crystal is outside TLK2501's operating range and should not be used. GTX_CLK rate is from 75MHz to 125 MHz. Please use a reference in this frequency range. 

    Reed said:
    3. Is there a problem using the 2.5G TLK2501 in a 3G optical module.

    This depends on the optical module. If optical module has CDR data rate set to 3G, then it will not lock to the 2.5G data from TLK2501's high speed side. 

    Reed said:
    4. For the TLK2501 50R external component, is there a need to optimize the circuit.

    To optimize 50 ohm characteristic impedance for serial and parallel sides, reduce component pad size to be as close to PCB trace width as possible.

    Reed said:
    5. Confirmation of technical support strength and methods.

    Unsure of what this questions means. Please clarify. 

    Reed said:

    6. Provide a software demo for TLK2501 on the FPGA side.

    We are unable to support this as we do not have FPGA demo available for TLK2501. Please see TLK2501 EVM and accompanying software GUI for configuration help. 

    Best,

    Charles