XIO2001 interoperability

Aaron Spaete

Other Parts Discussed in Thread: XIO2001

Team,

We are working with a customer with a PCIe to PCI XIO2001 bridge. Our board connects to customer boards over a Samtec High speed signal. We have had issues getting the TI bridge to consistently link and enumerate with either the eval board or the customer board. Our board has not had issues with other PCIe cards. Investigating we found the clock signal was out of PCIe spec. After terminating properly to HCSL the bridge enumerates when directly to the processor board. However I am still having issues enumerating the TI eval board. In the eval board configuration we have a 3in flex cable to go from our custom PCIe connector to a x1 connector slot. So over short distances, we are able to enumerate the XIO2001 but not with much added length. I've tested various PCIe cards (pericom PCI bridge , SATA, USB, Serial) and they work fine. Is there anything particular about the XIO2001 that may make it hard to work then another PCIe device? The eval board works fine in other applications, so I did something with the PCIe bus that the XIO2001 does not like but other devices tolerate. Any thoughts?"

"The TI bridge seem to dislike our LVDS clock driver. I've changed to a HCSL termination and resultes look improved. Thoughts?

Thoughts? "

"we are running our own homebrew Linux U-boot for the Freescale P1000 series processors.

Uboot hands it off to a higher OS but we are having the issue at boot. so we never get to the OS.

Playing with the SERDES drive strength in the CPU seems to improve the issue. Still investigating but the issue is never hot."

"

We are work with integrating a processor design with a add on card with the TI XIO2001 PCIe to PCI bridge. For whatever reason, Mu card has a hard time detecting and enumerating it consistently. The was with the eval and now the final add on card. I have had little trouble with other COTs PCIe cards.

Can you check on the following?

- Where can I get the "tuning " SW to setup ad change the EEPROM configuration?

- Can you ask around and see if there are an sensitive areas of the TI bridge?

- If possible, could I get and eval module. I think the SW is included.

What is really odd is placing a PCIe analyzer in series with the PCIe bus, everything looks find.

Any help would be appreciated?"

Regards,

Aaron

over 13 years ago

0 Lee E Myers over 13 years ago

TI__Intellectual 1710 points

Aaron,

I suspect the problem may not be related to the reference clock but rather the active termination of the P1011. I say this based on the fact that you report that the XIO2001 works okay behind the PCIe analyzer. In this case the XIO2001 is detecting the termination of the analyzer and not the P1011. The way a PCIe device handles receiver detect can be different for various silicon devices since the spec leaves it to the silicon vendor to decide on how to do receiver detect. As long as the far end termination as seen by the XIO2001 is within spec it will properly detect the termination and enter the polling state. Can you confirm that the P1011 active termination meets the spec? Instead of using a logic analyzer, try placing a scope on the transmitter of the XIO2001. If the XIO2001 is stuck in receiver detect you should see 1V on the scope and a periodic low going pulse.You can also try playing with the value of the AC coupling caps on the transmitter of the XIO2001. They can be in the range of 75-200nF with 100nF being the most commonly used value.

You can order the eval module from through ti.com. Just search on the XIO2001.

Regards,
Lee