DP83620: TXD_1, Pin 4, Input Only, pulls line to < 0.2V

Hello,

Note DP83620 is an older device and support is limited to datasheet. Please also note that TI US is approaching Good Friday holiday and will be back in office on Monday.

Sincerely,

Gerome

Hi Walter, 

I apologize for the delay in response. 
I have not heard any manufacturing issue on this part. 
However, I noticed that TXD_1 is an input pin and is not meant to be pulled up. Have you tried issuing 50MHz without the pullup and see if there are any issue? I wonder if pulling up the input pin when the PHY is in reset is damaging the PHY somehow. 
Has this issue only happened from this batch, or has other batches seen issue also?

Best,
J

Applying 50MHz clock was able to get the part to function on one board, but not two others.

Replacing the part with one from another batch found one from the other batch had this issue.

Hi Walter, 

The datasheet states that TXD_1 is not a strap pin so there should be no pulldown. 
Could there be a chance that the MAC is not functioning correctly and drives the TXD_1 pin low? Also, is the pin pulled low when the PHY is in reset?

Best,
J

via software I can reset the PHY and MAC individually using GPIO on the processor.  The pin was pulled low when either or both the PHY and MAC was in reset.  When PHY removed from the board, pin was always high at reset.

Hi Walter, 
Can you share your schematic so we can look at the reset circuitry?

Best,
J

PHY reset: 

MAC Reset: Stays in Reset until software is ready

Hi Walter, 

I apologize for the delay in response. 
Reset circuitry does not seem to have any issue. When there is no pullup on TXD_1, what is the voltage of TXD1? 
Also, you mentioned that supply 50MHz clock got one of the boards working. What issue does the PHY run into when the XI clock is provided?

Best,
J

On one board with 50 MHz applied, the PHY started working normally.  On another board, no difference, TXD was low

Hi Walter,

J has moved to another team so I will be taking over support for your issue. I see there is a concern that TXD_1 is pulling the signal line low which is unexpected.

From this thread I gather the order of events is as follows, please correct me if I'm wrong:

• MAC is powered on
• MAC sees 2.2K PU and provides 50MHz X1 signal to PHY
• After 50MHz reaches PHY, PHY is powered on

In this sequence you are seeing that the powered-down PHY is pulling the TXD_1 line low, preventing the MAC from providing the 50MHz clock correct? The power up timing diagram in the datasheet suggests a stable X1 prior to powerup so I want to check if this is being met.

Please note, as Gerome mentioned, DP83620 is an older PHY that is limited in support to existing public resources (Datasheet, E2E, app notes). If the design is still in development I recommend swapping to our newer DP83822. This PHY is fully supported and functionally similar to DP83620 as it supports fiber, MII, and RMII.

Best,

Shane

Shane,  The basis of the issue is the PHY pin is an input, but doesn't appear to be at power up.  The pin on the MAC muxt be high (strap pin that tells MAC to source the 50 MHz clock when high, uses external clock when low).  When the PHY pulls the pin low, the 50 MHz clock isn't sourced by the MAC.  I can manually set the MAC to output the 50 MHz by writing an internal register, but the PHY has still pulled the line low on 2 out of 3 parts.

Hi Walter,

Is the PHY powering up before the 50MHz is provided to X1? My concern is that if the PHY is not clocked at powerup it could be putting the PHY into an unknown state.

Best,

Shane

The yellow trace is the pull-up resistor going to the PHY TXD line, Purple is the 3.3V supply ramping up.  The bottom trace is POR_RESET#.  

The first trace shows when the PHY pulls the line down at power up.  The trace on the right is the expected response when the device works.  Note that it is random at power up whether the resistor is pulled low or follows the power supply. Pictures are done on the same board, same probe points. 

Once the pull-up resistor is pulled low, it stays low forever.

A PHY that was exhibiting this behavior was removed from the board, and the board appeared to have the pull-up ramp high every time.

There is a series resistor between the MAC and the PHY on the TxD line.  The pull-up is still in place on the MAC side of the resistor.  The board was powered cycle over 10 times and the pull-up resistor voltage followed the 3.3V rail up. With the PHY connected, one wouldn't get the same trace more than 3 power cycles in a row.

Hi Walter,

Can you show the X1 Crystal input in these plots as well?

Is there any option to adjust the timing of the TX_D pullup power rail and the PHY's VCC power rail, or are these both the same rail that is always powered together? If they are not the same rail, try allowing the strap to rise first, once stable allow VCC to rise.

A strong pulldown on TX_D pins is not expected behavior, so I believe something related to powering or clocking is putting the PHY in a bad state. As this is an older part, I'm unsure what exactly it could be.

If only one PHY or even one batch of PHYs showed this behavior it may be damaged parts, however if multiple batches are showing this it suggests a board dependency. One way to investigate whether this is the case could be to order a DP83620 evaluation kit and test the abnormal parts with a known-good platform.

Best,

Shane

Shane,

With the series resistor removed on the Txd line, I added a pull-up on the PHY side of the Txd line.

I have been able to get the PHY to stop pulling the line low at the 3rd rising edge of clock.  However, the MAC won't issue the clock if the line is pulled low. I am relying on the RMII bus timing based on the internal clock of the MAC. 

RMII timing has the data valid on the phy 4 ns prior to rising edge and 2 nsec after. 

One way to isolate the Txd line would be to insert a buffer from the MAC to the PHY. The MAC says the new data is valid before 14 nsecs from previous rising edge and the PHY wants 4 nsec minimum set-up time. before its rising edge. 

Hi Walter,

It makes sense that supplying the clock shows the expected behavior from the PHY, thank you for this update.

I'm confused how this powerup timing relates to the RMII bus timing you've mentioned. If you are isolating the TXD line between the MAC and PHY you may be able to let TX_D rise on the MAC side, the MAC will enable the CLK, then you can power on the PHY. Alternatively if there's a way to delay the powerup of the PHY to be after the latch-in of the MAC TXD strap you could try that as well.

Best,

Shane