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DP83848I: DP83848I SNI mode – RX_DV behavior and 10BT_SCR (Reg 0x1A) readback

Ryu Yamashita
Genius 4955 points

Part Number: DP83848I
Other Parts Discussed in Thread: DP83848-EP

Hi team,

Background: We are using DP83848IVV/NOPB in SNI mode (10 Mbps). Hardware strap settings per datasheet have been applied and reset is released correctly. However, we observe RX_DV (pin 39, RX_DV/MII_MODE) asserting during packet reception, even though the datasheet states “This pin is not used in SNI mode.” Additionally, when we read Register 26 (0x1A, 10Base‑T Status/Control, 10BT_SCR), we get 0x0001, while we expected 0x8000 as an indicator of SNI mode.
Questions:
  1. In SNI mode, is RX_DV guaranteed to be static (low/high) or high‑impedance, or can it still toggle/reflect internal receive‑valid activity even though it is “not used”? Please clarify the intended/guaranteed behavior for pin 39 in SNI.
  2. For 10BT_SCR (Reg 0x1A): what is the correct bit definition for bit[15] (0x8000), and under what conditions should it read as 1? Is 0x8000 a valid “SNI mode” confirmation check?
  3. Is any MDIO register write required to enter/lock SNI mode beyond reset strap configuration (e.g., forcing 10 Mbps, disabling auto‑negotiation), and do you recommend a specific register readback to confirm SNI operation?

Best Regards,
Ryu.

  • 0
    TI__Mastermind 26771 points

    Hi Yamashita-san,

    SNI mode requires TX_CLK and RX_CLK pins to output 10MHz clock. Is the customer seeing that? This would be the most clear indicator if the PHY is in SNI mode. I suggest to probe these pins instead of reading register values to confirm SNI mode. 


    I agree that register 0x1A bit15 should read 1 for SNI mode, so it does not seem like the PHY is in SNI mode. Does writing 0x8000 to this register put the PHY to show the correct behavior?

    To check the strap setting, could we take a look at the schematic?

    Best,

    J

  • 0 in reply to J
    Genius 4955 points

    Hi J,

    After checking again, we confirmed that the TX_CLK and RX_CLK pins are operating at 10 MHz, and Register 26 (10Base‑T Status/Control Register) is set to 0x8000. Based on these observations, we believe the device is operating in SNI mode. However, we still have a concern regarding the following point.

    In SNI mode, RX_DV is indicated as “not used,” but we observe that RX_DV is asserted during data reception. The datasheet states, “This pin is not used in SNI mode.” Could you please clarify whether RX_DV may still be asserted during data reception even in SNI mode?

    In the datasheet, under “AC Timing Requirements,” T2.14.2 is described as “RX_CLK fall to RXD_0, RX_DV.”
    However, in “Figure 5-14. 10 Mb/s Serial Mode (SNI) Receive Timing,” T2.14.2 is illustrated as being referenced from the rising edge of RX_CLK.

    Is it correct to understand that the figure is incorrect?

    From my understanding, the correct interpretation would be that the arrow for T2.14.2 should start from the end of the arrow for T2.14.1, rather than from the rising edge of RX_CLK.

    We would appreciate your guidance on this matter.

    Best Regards,
    Ryu.

  • +1 in reply to Ryu Yamashita
    TI__Mastermind 26771 points

    Hi Yamashita-san,

    I agree with your opinion. It seems like the figure in the datasheet is wrong. Please check out Figure 4-15 of DP83848-EP datasheet for the correct figure.


    https://www.ti.com/lit/ds/symlink/dp83848-ep.pdf

    Best,

    J

  • 0 in reply to J
    Genius 4955 points

    Hi J-san,

    Thank you for your reply.
    Could you please answer the following questions as well?

    Ryu Yamashita said:
    In SNI mode, RX_DV is indicated as “not used,” but we observe that RX_DV is asserted during data reception. The datasheet states, “This pin is not used in SNI mode.” Could you please clarify whether RX_DV may still be asserted during data reception even in SNI mode?

    Best Regards,
    Ryu.

  • +1 in reply to Ryu Yamashita
    TI__Mastermind 26771 points

    Hi Yamashita-san,

    Because this device is old, the datasheet is the only available documentation. I could not find information on documentation but I observed on the evaluation board that RX_DV is asserted periodically in SNI mode. Because the datasheet specifies that this pin is not needed so I do not anticipate for this pin to be used, but please note that it can be asserted.

    Best,

    J