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SN65DSI84: Understanding DSI Mode Flags

Shwetha Nayak
Intellectual 410 points

Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hi Team,

We are working on upstreaming support for a dual-link LVDS panel AUO G133HAN0  using the bridge SN65DSI84 on a Qualcomm platform.

Below is the link for panel datasheet

https://datasheet4u.com/pdf/1257948/G133HAN01.0.pdf 

 During initial bring-up, TI had provided a working configuration with specific hardcoded register values and DSI mode flags(using DSI-tuner), which helped us validate the display successfully.However, as part of upstreaming, we are moving towards a generic implementation based on panel timings instead of hardcoded values. For this, we adopted the latest changes suggested by the upstream bridge driver maintainer.Attaching the patches for your reference:
https://lore.kernel.org/all/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a…

https://lore.kernel.org/all/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-2-2e15f5a9a6a…
https://lore.kernel.org/lkml/20260309-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v2-1-e6aaa7e1d1…

While doing this, we observed that the DSI mode flags have a direct impact on the stability of the LVDS output. the default configuration which is available in the existing upstramed driver is as below (NON-WORKING)
MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET;

From the above mode some mode are removed and below is the working DSI MODE FLAGS configuration:
MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_NO_HSA |
MIPI_DSI_MODE_NO_EOT_PACKET;

With this updated configuration (i.e., without burst mode and with HFP/HBP enabled), the LVDS panel operates stably in dual-link mode.

We would like to understand the dependency of DSI mode flags (especially MIPI_DSI_MODE_VIDEO_BURST and the handling of HFP/HBP intervals) on the SN65DSI84 for dual-link LVDS operation.

So my main question is that why after removing the MIPI_DSI_MODE_VIDEO_BURST, 
MIPI_DSI_MODE_VIDEO_NO_HFP, MIPI_DSI_MODE_VIDEO_NO_HBP made the LVDS display working? 

This clarification will help us justify the correct dsi->mode_flags selection while upstreaming and ensure alignment with the bridge’s expected behavior.

Thanks for your support.

Regards,

Shwetha Nayak

  • 0
    TI__Mastermind 29020 points

    Hi Shwetha,

    1. Could you please tell us what the MIPI_DSI_MODE_VIDEO_NO_HBP/HFP is changing?

    2. The DSI84 device still needs to be programmed for specific timings to match the incoming DSI video and the display timings required. The device should be programmed for the DSI clock rate and LVDS clock rates used. And the initialization sequence should be followed which includes the clock to be in HS mode, not LP11 state.

    3. Could you also share that whether there are errors in the not-working case showing in the 0xE5 register?

    4. If you program the device in the specific display timings with test pattern mode, is it working as expected? Please check with test pattern with those timings, and then as a next step, change back to DSI input video.


    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Intellectual 410 points

    Hi Ikram,

    Thank you for your response.

    1. Could you please tell us what the MIPI_DSI_MODE_VIDEO_NO_HBP/HFP is changing?

    => When the MIPI_DSI_MODE_VIDEO_NO_HBP, MIPI_DSI_MODE_VIDEO_NO_HFP and MIPI_DSI_MODE_VIDEO_BURST is enabled we don't see anything in the display just the backlight could be seen.

    2. The DSI84 device still needs to be programmed for specific timings to match the incoming DSI video and the display timings required. The device should be programmed for the DSI clock rate and LVDS clock rates used. And the initialization sequence should be followed which includes the clock to be in HS mode, not LP11 state.

    => Yes, all the initialization sequence and register programming are taken care which is current and verified from DSI Tuner.

    3. Could you also share that whether there are errors in the not-working case showing in the 0xE5 register?

    => In non-working case I do not see any errors in 0xE5 below is the register dump

    i2cdump -y 1 0x3d
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 14 00 00 00 00 00 00 00 00 00 41 0e bc 18 01 13    ?.........A?????
10: 25 37 00 00 00 00 00 00 46 62 04 a8 00 00 1c 84    %7......Fb??..??
20: 1c bf 04 a8 1e 70 02 1e 00 00 04 a8 08 12 1b ac    ?????p??..??????
30: 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 b0    ...........?...?
40: 00 50 10 7e 79 70 70 70 70 00 80 00 00 00 00 00    .P?~ypppp.?.....
50: 00 00 02 0d 00 00 00 00 00 00 00 00 00 00 00 00    ..??............
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 01 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ??..............
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 c0 00 00 00 03 02 00 18 38 61 00 00    ....?...??.?8a..
a0: 00 00 a0 a0 08 04 00 00 00 00 00 40 00 00 40 14    ..????.....@..@?
b0: 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00    ..........?.....
c0: 00 00 00 00 00 00 0a 00 00 03 00 00 02 00 01 04    ......?..?..?.??
d0: 30 ff 80 80 80 00 08 00 00 00 00 00 00 00 88 01    0.???.?.......??
e0: 80 78 00 00 00 00 fd 00 00 00 52 46 00 00 00 00    ?x....?...RF....
f0: 95 04 ff 00 00 00 00 00 00 10 7d aa 1c 00 b0 00    ??.......?}??.?.

    4. If you program the device in the specific display timings with test pattern mode, is it working as expected? Please check with test pattern with those timings, and then as a next step, change back to DSI input video.

    => If above flags like NO_HBP and NO_HFP is enabled even with the test pattern enabled we are not able to see anything on display expect the backlight

  • 0 in reply to Shwetha Nayak
    TI__Mastermind 29020 points

    Hi Shwetha,

    As a first step, we would recommend using test pattern mode and get the register configurations with the DSI Tuner tool. This will require a RECLK or DSI clock as source. And a working test pattern will prove that the display is working with the programmed timings.

    I am not familiar with the "MIPI_DSI_MODE_VIDEO_NO_HBP, MIPI_DSI_MODE_VIDEO_NO_HFP and MIPI_DSI_MODE_VIDEO_BURST" entries. Are these programmed on the SoC? Note that the HBP, HFP, and similar timings will need to be enabled and programmed based on the display specifications.

    Most displays will require a certain range of horizontal front porch, horizontal back porch and horizontal sync pulses to meet the blanking requirements. The working timings should be included in the displays' datasheets. Please refer to those specifications to program both the SoC and DSI84.


    Best regards,
    Ikram