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DP83867IR: DP83867IR internal test mode

Katsufumi Miyaji
Prodigy 30 points

Part Number: DP83867IR

Dear Technical Support Team,

I have set the STRAP configuration for the RX_CTL pin of the DP83876IR to Mode 1.

In Note (2) of Table 7-5 in the datasheet, the description of bit [7] in “Configuration Register 4” includes the term “internal test mode.”

Q1: Could you please explain what “internal test mode” is?

Q2: Is 1000Base-T communication possible even if bit [7] of “Configuration Register 4” remains set to 1?

Q3: If bit [7] of “Configuration Register 4” is not set to 0, what kind of problems might occur?

 

note2.png

CFG4.png

Best Regards

Katsufumi

  • 0
    TI__Mastermind 26771 points

    Hi Katsufumi-san,

    1. We cannot disclose what internal test mode does.

    2. Yes the PHY can function normally even when it is in internal test mode. It will do 1G communication without any issue.

    3. You can set it to 0 but as this is not the only bit that outs the PHY in the internal test mode. Register 0x6F[8] also indicates if the PHY is in test mode so if that bit is not set, there is no need to clear this bit to 0.

    Best,

    J

  • 0 in reply to J
    Prodigy 30 points

    Hi J-san

    Thank you for your response.

    According to the datasheet, since 0x6F[8] has a default value of 0 and is read-only (RO), it seems that the only way to disable internal test mode is to set 0x31[7] to 0. Is this understanding correct?

    Is there another method, such as setting 0x6F[8] to 1?

    Best Regards

    Katsufumi

  • 0 in reply to Katsufumi Miyaji
    TI__Mastermind 26771 points

    Hi Katsufumi-san, 


    Katsufumi Miyaji said:
    According to the datasheet, since 0x6F[8] has a default value of 0 and is read-only (RO), it seems that the only way to disable internal test mode is to set 0x31[7] to 0. Is this understanding correct?

    Yes, this is correct. 

    Katsufumi Miyaji said:
    Is there another method, such as setting 0x6F[8] to 1?

    This is not possible. 

    However, please note that writing 0 to 0x31[7] is only necessary when 0x6F[8] is set to 0. The datasheet specifies that the default value for this bit is 0 but this is not entirely true since the reset value depends on the strap pin. If RX_CTL pin is strapped to mode 1 or 2, 0x6F[8] may set to 0. Otherwise, this bit should set to 1 by default. 

    Best,
    J

  • 0 in reply to J
    Prodigy 30 points

    Hi J-san

    Thank you for your response.

    Your explanation helped me resolve the issue.

    Best Regards

    Katsufumi