DS90UB954-Q1: Technical Support: Register Configuration for DS90UB954-Q1 (2-lane CSI-2) with DS90UB933-Q1 - RAW12 Coaxial

We are currently working with the DS90UB933-Q1 (Serializer) and DS90UB954-Q1 (Deserializer) chipset. We need assistance with the specific register initialization sequence for the following hardware configuration:

Hardware Setup & Requirements:

• Interface: Single-ended Coaxial 
• Input Resolution: 1MP (1280x800) from the camera.
• Target Output: 30 FPS.
• Target Data Type: RAW12
• Verified Connections: Pins 11 and 12 (CSI_CLK0) are connected to our SoC.

Reference Project Data: In a previous project with a similar architecture, we used the following register values as a reference 

Register ID	Register name	Current value
0x01	Reset	0x01
0x1F	CSI_PLL_CTL	0x02
0x4c	FPD3_PORT_SEL	0x01
0x58	BCC_CONFIG	0X58
0x5c	SER_ALIAS_ID	0xE8
0x5D	TargetID[0]	0x20
0x65	TargetAlias[0]	0x80
0x5e	TargetID[1]	0x0A
0x66	TargetAlias[1]	0xC0
0x5F	TargetID[2]	0x80
0x67	TargetAlias[2]	0x90
0x7C	PORT_CONFIG2	0x00
0x6e	BC_GPIO_CTL0	0x99
0x70	RAW10_ID	0x2B
0x71	RAW12_ID	0x2C
0x6D	PORT_CONFIG2	0x7E
0x12	PGEN_COLOR2	0x13
0x33	CSI_CTL	0x21
0x20	FWD_CTL1	0x00
0x21	FWD_CTL2	0x81
0x0f	PGEN_VFP	0x0F
0x14	PGEN_COLOR4	0x55
0x15	PGEN_COLOR5	0x57
0xBC	FV_MIN_TIME	0x00

Questions:

1. Can you confirm if this configuration is optimized for RAW12 over 2 MIPI lanes given our 1MP@30FPS target?

2. Specifically, regarding register 0x33, is 0x21 correct for 2-lane operation with continuous clock, or should we adjust the lane count bits?

3. Are there any other mandatory registers settings  you would recommend to ensure a stable CSI-2 throughput?

If you require any additional information regarding our system architecture or schematics to provide an optimized solution, please let us know.

Thanks in advance

Rodrigo Rubio - Software Enginer - Valeo