Part Number: DS90UB913A-Q1
Other Parts Discussed in Thread: DS90UB913A-CXEVM, DS90UB914A-CXEVM
Hello,
I am using a DS90UB913A/DS90UB914A pair (currently on evaluation boards via DS90UB913A-CXEVM and DS90UB914A-CXEVM), but I have the DOUT+/- pins from DS90UB913A pins tied to TD+/- on an SFP module (1Gbps capable) and then the SFP connected via single mode fiber to another SFP with its RD+/- pins connected to the RIN+/- pins on the DS90UB914A. I am using the DS90UB913A/DS90UB914A in 12-bit LF mode, with a PCLK of 27MHz going into the DS90UB913A. I am only using 8 bits of data, with both HSYNC and VSYNC. I believe this should yield an overall high-speed bit rate of 28*27MHz = 756Mbps. The SFP modules are plugged into SFP breakout boards with SMA connections for TD+/- and RD+/-. The physical cable connections between the DS90UB913A-CXEVM/DS90UB914A-CXEVM and the SFP breakout boards are standard 50 Ohm Coax cables that are about 1 foot in length.
When hooked up to the SFP modules, I see a lock on the DS90UB914A (via the lock LED on the eval board, and measuring this with an oscilloscope shows it to be steady in the logic high state. I am also seeing a 27MHz PCLK (which is the same as the PCLK into DS90UB913A) out of the DS90UB914A which indicates to me that the deserializer is locked and recovering the proper clock from the serializer. However, the issue is that I see no HSYNC, VSYNC or any data bits. HSYNC, VSYNC and D0-D7 are all stuck low. Reading the registers of the DS90UB913A, bit 0 (LINK Detect) of the "General Status" Register (Address 0x0C) is logic low - indicating a fault of some kind. If I take the SFP modules out of the setup and wire the DS90UB913A outputs directly to the DS90UB914A inputs, everything works properly and I am able to recover PCLK, HSYNC, VSYNC, and D0-D7.
I understand that the SFP connections will prevent the back-channel from operating between the DS90UB914A and the DS90UB913A. I had read in other forum posts that these parts are able to operate without the back channel. Is the back channel still required during initialization, to synchronize these two parts, in order to establish the link? If not, shouldn't these two parts work over an SFP connection scheme as described above?
Any insight you can provide into resolving this issue would be greatly appreciated. I have attached the register values that I am reading from the two devices.
Thank you,
Devin Mullen