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DP83630: DP83630-SFP Module Interface

Part Number: DP83630
Other Parts Discussed in Thread: LAUNCHXL2-570LC43, , DP83640

Hi,

We are trying to interface DP83630 with SFP transceiver module using TI LAUNCHXL2-570LC43 by replacing RJ45 connector in the eval board with SFP module.Is this method compatible? If yes,what all changes do we need to do in the eval board for achieving this?Currently we tried to interface,but transmission is not happening.Data is coming from the PHY,but not transmitting through SFP.

 

  • Hi,

    For fiber network, it will have to be AC coupled to the fiber transceiver.  On the Phy side, the signals will be pulled up to the 3.3V supply via 50 Ohm terminations as shown below.

    The DP83630 supports both Twister Pair (100BASE-TX and 10BASE-T) and Fiber (100BASE-FX) media. The port may be configured for Twisted Pair (TP) or Fiber (FX) operation by strap option or by register access. At power-up/reset, the state of the RX_ER pin will select the media for the port. The default selection is twisted pair mode, while an external pull-down will select FX mode of operation. Strapping the port into FX mode also automatically sets the Far-End Fault Enable, bit 3 of PCSR (16h), the Scramble Bypass, bit 1 of PCSR (16h) and the Descrambler Bypass, bit 0 of PCSR (16h). In addition, the media selection may be controlled by writing to bit 6, FX_EN, of PCSR (16h).

    We also need to look the signaling requirement of the SFP transceiver. The RD+/- pins are designed to detect LVPECL levels of VDD - 0.9V and VDD - 1.7V.  In other words, based on a 3.3V supply, signals above 2.4V would be seen as high and signals below 1.6V would be seen as low.  The design has some margin to these values, but these are the nominal thresholds.

    The DP83630 d signal detect (SD) input are designed to accept LVPECL levels so AC coupling is generally not necessary for the SD pin. 

    Thanks

    David

  • Hi,.

    Could you please clarify;

    1. Is the DP83630 TX output (in 100BASE-FX mode) fully compliant with LVPECL input requirements of typical SFP modules, or is an external level shifting / buffer stage required?
    2. Do you have a reference schematic or EVM design where DP83630 is successfully interfaced to an SFP module?
    3. What is the expected TX differential swing and common-mode voltage at the PHY output in FX mode?
    4. Are there any specific SFP modules validated by TI for use with DP83630?
    5. Should any external biasing network be added after AC coupling to meet LVPECL thresholds?

    This will help us confirm whether the issue is due to signal level incompatibility or configuration.

    Thanks

  • Hi,

    For the DP83630 FX interface, the transmit driver does not output LVPECL levels.  Therefore, the TD+/- pins must be AC coupled and properly terminated to interface correctly with an LVPECL compatible fiber transceiver. 

    I don't have a specific design of DP83630 to an SFP module, but if you take a look at this e2e thread, https://e2e.ti.com/support/processors-group/processors/f/processors-forum/379564/changing-dp83630-phy-to-100basefx?tisearch=e2e-sitesearch&keymatch=DP83630, DP83630 is able to support the fiber interface.

    You can also see this E2E thread which we had customer successfully interfaced DP83640 to the AFBR-5803AZ-100FX module.

    For TX Differential Swing, please see the spec below

    For external biasing network, please see Figure 9-2 from my previous response.

    Thanks

    David