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TPD4E001: TPD4E001: Vcc connection and the effect on I/O capacitance

G
Prodigy 30 points

Part Number: TPD4E001
Other Parts Discussed in Thread: STRIKE

I am planning to use TPD4E001 for ESD protection on some GPIO and SPI ports (3.3V IO). 

According section 7.2.2 of the datasheet, I can opt to not connect the IC's Vcc pin to system power supply, while a 0.1uF capacitor is still recommended to add at the Vcc pin. 

My question is: would leaving Vcc NOT connected to system rail have any negative impact the capacitance seen at the I/O pin (i.e. larger input capacitance)? 

My rationale is that, since there is no Vcc to reverse bias the hidding/steering diode that sits between an IO pin and Vcc,  the IO pin might see the full capacitance that is connected to the Vcc.

Thank you in advance for your help!

G

 

TPD4E001--Section-7-2-2.png

 

 

  • 0
    TI__Expert 5880 points

    Hi G,

    Your reasoning seems right to me. I will need to confirm with the team.

    On a separate note, this is an old device, is there a reason why you are not choosing a newer released device with lower capacitance?

    Best,

    Bryan

  • 0 in reply to Bryan Rodriguez de San Miguel
    Prodigy 30 points

    Hi Bryan,

    Thank you for your reply. Could you recommend a newer released device? (I am unaware that TPD4E001 is an old device)

    Best,

    G

  • 0 in reply to G
    TI__Expert 5880 points

    Hi G,

    TPD4E05U06 has a lower capacitance. I don't know your required specs so let me know if this works.

    Best,

    Bryan

  • 0 in reply to Bryan Rodriguez de San Miguel
    Prodigy 30 points

    Hi Bryan,

    The part you suggested should work. Thank you!

    Regarding my original question about tpd4e001, could you still follow up with you team? (it would be good to know for my future reference)

    Best,

    Grant

  • 0 in reply to G
    TI__Expert 5880 points

    Hi G,

    I have followed up with the team. Please give me a couple of days to gather their feedback.

    Best,

    Bryan

  • 0 in reply to Bryan Rodriguez de San Miguel
    Prodigy 30 points

    Thank you Bryan. Have a good weekend!

  • 0 in reply to G
    TI__Expert 5880 points

    Hi G,

    I hope you had a good weekend. Please see comments below regarding your question:

    If VCC is not connected at all, I don’t think any cap on VCC pin is needed as well.

    I understand your comment that cap might increase since the upper diode at I/O is no longer reverse biased.

    But the increase may not be significant since D1 is in series which is reverse biased.

    So effectively, the I/O pins might see 0V bias cap instead of 2.5V reverse bias (in absence of 0.1uF cap).

    With 0.1uF cap still on board and VCC disconnected, you’re correct about I/O pins seeing entire 0.1uF cap.

    This is the feedback provided by our backend engineers. I am still trying to figure out why datasheet recommends keeping it there. Something I wanted to ask is why is VCC not connected to the VCC pin? What is your application?

    Best,

    Bryan

  • 0 in reply to Bryan Rodriguez de San Miguel
    Prodigy 30 points

    Hi Bryan,

    Thank you and your colleague for the reply. For my application, I typically need to protect some board I/Os (connectors) that passes through SPI/UART/I2C/GPIO.  Sometimes the connectors passes through VCC and some times they do not.

    I have a follow up question regarding TVS selection:

    I know that many of those TVS arrays comes with two flavors, some with VCC pin and some without. My question is, what is the purpose for the Vcc pin on a TVS array? Is it intended to protect Vcc rail from an ESD event, or it is there so that an ESD strike on an I/O pin can be re-directed to the Vcc rail and can be better absorbed by the capacitance on the Vcc rail? It seems to be the latter based on the TPD4E001 datasheet.

    And to follow up to my question above, how should I go about choosing a TVS array (one with Vcc vs one without)?

    Thank you again!

    Grant

  • +1 in reply to G
    TI__Expert 5880 points

    Hi G,

    Your understanding is right. It is there so that an ESD strike on an I/O pin can be re directed to the VCC rail and be better absorbed by the capacitance on the VCC rail. This results in lower clamping voltage on the I/O pin.

    Normally, the newer TVS diodes we are releasing do not have VCC in their configuration meaning the strike goes directly into ground. This is just a simpler, safer path to ground.

    Best,

    Bryan

  • 0 in reply to Bryan Rodriguez de San Miguel
    Prodigy 30 points

    Thank you very much Bryan!

    Grant

  • 0 in reply to G
    TI__Expert 5880 points

    Hi G,

    I was able to talk to another designer, and he mentioned that the additional capacitor in the VCC pin helps with the first peak of an ESD strike. The drawback is that you will see additional capacitance in the IO line.

    Hopefully this makes sense.

    Best,

    Bryan