DP83848K: Ethernet PHY reset issue

Hi Jomon,

To preface, DP83848 is an older part with support limited to existing documentation. If there is still an option to switch to a newer device I would recommend using DP83826A. DP83826A is similar in function to DP83848 and is fully supported. Now to address the issue:

1. Does register access work in cases where the initialization is successful? 

2. By 'boot' are you referring to a hardware reset or a power cycle of the board?

3. Is X1 stable on powerup? The powerup timings diagram suggests a stable clock at powerup:

Best,

Shane

Hi,

Does register access work in cases where the initialization is successful? 
      On the same board, register access works when initialization is successful. We have already verified this using U-Boot MII commands. However, on the same board, it does not work when initialization fails.

By 'boot' are you referring to a hardware reset or a power cycle of the board?
     It is a power cycle

Is X1 stable on powerup? The powerup timings diagram suggests a stable clock at powerup:
     From the DSO analysis it is stable. For an experiment we tried to disconnect the 50 MHz clock line from PHY but still we can able to access the MDIO communication if it in good state.

Hi Jomon,

In the failing state, is DP83848 still able to link up on the MDI? Since there is no register access you may need to check the LED_LINK for this.

Do you see any differences in the power sequence in passing vs failing states?

Jomon Thomas said:

we tried to disconnect the 50 MHz clock line from PHY but still we can able to access the MDIO communication if it in good state.

To confirm, you're able to disconnect the X1 input of the PHY and it will still respond at some power-ups? I would double check that this clock is provided at powerup and is constantly supplied to the PHY.

Do you see activity on the MDIO bus in the failing state or is the bus silent?

Do you see this on all of your boards or only some of them?

Does replacing the DP83848 PHY have any effect on the behavior?

For context on my questioning, the fact that the MDIO communication is failing suggests a hardware issue. Since this is power-cycle dependent I'm mostly looking at how the PHY is powered up.

Best,

Shane

Hi,

Q. Do you see any differences in the power sequence in passing vs failing states?
    No, we are using the same power procedure for both successful and failed cases.

Q. To confirm, you're able to disconnect the X1 input of the PHY and it will still respond at some power-ups? I would double check that this clock is provided at powerup and is constantly supplied to the PHY.

     A. Yes, based on our experiments, MDIO/MDC communication works without a 50 MHz clock source. No clock is provided to the PHY during startup, as it is isolated at the hardware level.

Q. Do you see activity on the MDIO bus in the failing state or is the bus silent?
   A. We observed MDC activity before resetting the PHY. During Linux code analysis, I found that this behavior is normal when using the PHY-level reset method in device tree configuration.

Also, MDIO communication is multi-node, where the master communicates with different PHY devices and can poll their registers, correct? In that case, will MDIO activity affect the PHY chip?

Q. Do you see this on all of your boards or only some of them?
    A. The project started around 1.5 years ago. During that time, we used the development version of the board. Many developers worked on it, and both unit testing and system testing were conducted regularly during the development phase. However, we did not face this particular issue. And those board are still working properly.

Now, we have moved to the production version of the board, with changes to address EMI/EMC issues. This issue has only been observed in the production boards and not all board showing this issue.

Hi,

I have already created an AM623-based thread to discuss this issue. The Linux-based discussion is ongoing, and I am adding this here for reference.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1637182/am623-how-to-change-the-ethernet-phy-reset-sequence-with-cpsw-davinci-mdio-driver

Hi Jomon,

If the previous iteration of the board did not have this issue, I'd like to know what was changed moving to the production version. It seems this fixed EMI issues but is now causing this communication issue.

Best,

Shane