AM2634: AM2634 MAC TX Not Working & DP83869 PHY Loopback Failure (MDIO OK) And Not Pinging.

Chinchetti Abhishek

Part Number: AM2634
Other Parts Discussed in Thread: SYSCONFIG, DP83869

Hi Team,
We are currently working with the below TI components on our custom board:

MAC: AM2634COLFHAZCZR
PHY: DP83869HMRGZR

We are facing an issue where the Ethernet interface is not working as expected, although the same software setup works fine on the TI EVM.
Observations:

MDIO/MDC communication is working properly, and we are able to read/write PHY registers.
A stable 25 MHz clock is present at the PHY.
On the MAC side, we are not seeing any activity on TXD[0:3] and TX_CTL — MAC is not transmitting data.
The PHY is responsive over MDIO, but PHY loopback is not working, and no proper TX output is observed.
On the RX side, behavior is intermittent — occasionally we are able to see data.

Configuration:

Interface: RGMII
External 25 MHz clock to PHY
MDIO verified
RX_CTRL (MIRROR_EN) configured similar to EVM

Software:Screenshot 2026-04-25 120732.zip
We are using the ENET_LWIP_CPSW example for AM2634.
The same code works correctly on the TI EVM (ping and loopback both working), but on our custom board:

Ping is not working
PHY loopback is failing

Tests Done:

Verified schematic connections with EVM reference
Checked power rails and stability
MDIO communication confirmed
PHY loopback test → Failed
MAC loopback test → Passed

Clarifications Needed:

What could be the reason for no TX activity from MAC even though MDIO is working?
Why would PHY loopback fail in this condition?
Are there any specific MAC or PHY register configurations required to enable TX?
Are there any RGMII timing or skew requirements we should specifically verify?
What would be the recommended approach to isolate whether the issue is from MAC, PHY, or hardware interface?

We have attached the custom board schematic and configuration files for your reference.BLIS_CUSTOM_BOARD_REV02_PDF.pdf

5 months ago

0 Shaunak Deshpande 5 months ago

TI__Mastermind 27122 points

Hi,

Since the MAC Loopback passes, this is most certainly not an issue with CPSW completely dead. So CPSW Core, DMA Path, Interal host side are alive. Failure occurs after that meaning some external RGMII/PHY, board-config path is broken.

Q1. Have you adapted sysconfig ethphy to custom design changes such as PHY setting changes if needed?

Q2. Is there any difference between the TI EVM schematic and the custom board schematic in terms of anything that comes after the CPSW MAC level?

Q3. Can you help analyse the below:

1. Get a CPSW register dump of working case (TI EVM + TI Driver with the SDK loopback application for MAC and PHY)

2. Get a CPSW register dump of non-working case (custom HW).

If there is no difference in the above regs, then the issue is most certainly pointing that you need to migrate your SW to match your custom HW changes.

Regards,
Shaunak

+1 Chinchetti Abhishek 5 months ago in reply to Shaunak Deshpande

Prodigy 30 points

Hi Shaunak,

Thanks for the reply.

For the first point, please refer to the attached image.

There is no change between the custom board and the EVM on the MAC side. I have already shared the schematic—kindly review it and suggest if any changes are required.

Please find the requested register dumps below:

Working case: EVM_PHY_REG.txt

Fullscreen EVM_PHY_REG.txt Download

==========================
      ENET LWIP App
==========================
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2
Mdio_open:320
Open MAC port 1
PHY 0 is alive

============= DP83869 FULL DUMP =============
Reg[0x00] (BMCR              ) = 0x1140
Reg[0x01] (BMSR              ) = 0x796D
Reg[0x02] (PHYIDR1           ) = 0x2000
Reg[0x03] (PHYIDR2           ) = 0xA0F1
Reg[0x04] (ANAR              ) = 0x01E1
Reg[0x05] (ANLPAR            ) = 0xCD81
Reg[0x06] (ANER              ) = 0x006F
Reg[0x07] (ANNPTR            ) = 0x2001
Reg[0x08] (ANNLPTR           ) = 0x6001
Reg[0x09] (GEN_CFG1          ) = 0x0200
Reg[0x0A] (GEN_STATUS1       ) = 0x0000
Reg[0x0B] (RESB              ) = 0x0000
Reg[0x0C] (RESC              ) = 0x0000
Reg[0x0D] (REGCR             ) = 0x401F
Reg[0x0E] (ADDAR             ) = 0x0000
Reg[0x0F] (1KSCR             ) = 0xF000
Reg[0x10] (PHY_CONTROL       ) = 0x5048
Reg[0x11] (PHY_STATUS        ) = 0x7C02
Reg[0x12] (INT_MASK          ) = 0x0000
Reg[0x13] (INT_STATUS        ) = 0x1C40
Reg[0x14] (GEN_CFG2          ) = 0x29C7
Reg[0x15] (RX_ERR_CNT        ) = 0x0000
Reg[0x16] (BIST_CONTROL      ) = 0x0000

------ C22 EXTENDED REGISTERS ------
Reg[0x17] (STATUS2                       ) = 0x0040
Reg[0x18] (LEDS_CFG1                     ) = 0x5160
Reg[0x19] (LEDS_CFG2                     ) = 0x4444
Reg[0x1A] (LEDS_CFG3                     ) = 0x0002
Reg[0x1E] (GEN_CFG4                      ) = 0x0212
Reg[0x1F] (GEN_CTRL                      ) = 0x0000
Reg[0x25] (ANALOG_TEST_CTRL              ) = 0xCD81
Reg[0x2C] (GEN_CFG_ENH_AMIX              ) = 0x0000
Reg[0x2D] (GEN_CFG_FLD                   ) = 0x401F
Reg[0x2E] (GEN_CFG_FLD_THR               ) = 0x0000
Reg[0x31] (GEN_CFG3                      ) = 0x6C02
Reg[0x32] (RGMII_CTRL                    ) = 0x0000
Reg[0x33] (RGMII_CTRL2                   ) = 0x0000
Reg[0x37] (SGMII_AUTO_NEG_STATUS         ) = 0x0040
Reg[0x39] (PRBS_TX_CHK_CTRL              ) = 0x4444
Reg[0x3A] (PRBS_TX_CHK_BYTE_CNT          ) = 0x0002
Reg[0x43] (G_100BT_REG0                  ) = 0xA0F1
Reg[0x4F] (SERDES_SYNC_STS               ) = 0xF000
Reg[0x55] (G_1000BT_PMA_STATUS           ) = 0x0000
Reg[0x6E] (STRAP_STS                     ) = 0x0000
Reg[0x71] (DBG_PRBS_BYTE_CNT             ) = 0x6C02
Reg[0x72] (DBG_PRBS_ERR_CNT              ) = 0x0000
Reg[0x7B] (DBG_PKT_LEN_PRBS              ) = 0x0000
Reg[0x7C] (DBG_IPG_LEN                   ) = 0x0000

------ CLAUSE45 EXTENDED REGISTERS ------
Reg[0x0086] (ANA_RGMII_DLL_CTRL            ) = 0x0377
Reg[0x00A0] (ANA_LD_TXG_FINE_GAINSEL_AB    ) = 0x0806
Reg[0x00A1] (ANA_LD_TXG_FINE_GAINSEL_CD    ) = 0x0808
Reg[0x00A2] (ANA_LD_FILTER_TUNE_AB         ) = 0x1010
Reg[0x00A3] (ANA_LD_FILTER_TUNE_CD         ) = 0x1010
Reg[0x00C6] (ANA_PLL_PROG                  ) = 0x0000
Reg[0x00D6] (SGMII_TESTMODE                ) = 0x0000
Reg[0x00E9] (DSP_HYBRID_CFG2               ) = 0x9F22
Reg[0x00FE] (LOOPCR                        ) = 0xE721
Reg[0x0134] (RXF_CFG                       ) = 0x1000
Reg[0x0135] (RXF_STATUS                    ) = 0x0000

============= END OF DUMP =============
[0]: Starting lwIP, local interface IP is 192.168.1.200
[LWIPIF_LWIP] NETIF INIT SUCCESS
Host MAC address-0 : 70:ff:76:1d:ec:f2
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 192.168.1.200
UDP server listening on port 5001
[0] link_callback==UP
      8. 32s : CPU load =   7.46 %
     13. 32s : CPU load =   1.68 %

Non-working case: CUSTOM_PHY_REG.txt

Fullscreen CUSTOM_PHY_REG.txt Download

==========================
      ENET LWIP App
==========================
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 4 To 2
Mdio_open:320
Open MAC port 1
PHY 0 is alive

========= FULL PHY DUMP =========

---- STANDARD PHY REGISTERS (0x00–0x1F) ----
Reg[0x00] (BMCR) = 0x3100
Reg[0x01] (BMSR) = 0x796D
Reg[0x02] (PHYID1) = 0x2000
Reg[0x03] (PHYID2) = 0xA0F3
Reg[0x04] (ANAR) = 0x01E1
Reg[0x05] (ANLPAR) = 0xCDE1
Reg[0x06] (ANER) = 0x006F
Reg[0x07] (ANNPTR) = 0x2001
Reg[0x08] (ANNPRR) = 0x4006
Reg[0x09] (RES9) = 0x1200
Reg[0x0A] (RESA) = 0x3800
Reg[0x0B] (RESB) = 0x0000
Reg[0x0C] (RESC) = 0x0000
Reg[0x0D] (RESD) = 0x0000
Reg[0x0E] (RESE) = 0x0000
Reg[0x0F] (RESF) = 0xF000
Reg[0x10] (PHYCR) = 0x5028
Reg[0x11] (PHYSTS) = 0xBF02
Reg[0x12] (MICR) = 0x0000
Reg[0x13] (MISR) = 0x0000
Reg[0x14] (PAGESEL) = 0x29C7
Reg[0x15] (FCSCR) = 0x0000
Reg[0x16] (RECR) = 0x0000
Reg[0x17] (PCSR) = 0x0040
Reg[0x18] (RBR) = 0x6150
Reg[0x19] (LEDCR) = 0x4000
Reg[0x1A] (PHYCTRL2) = 0x0002
Reg[0x1B] (EDCR) = 0x0000
Reg[0x1C] (RES1C) = 0x0000
Reg[0x1D] (RES1D) = 0x0000
Reg[0x1E] (RES1E) = 0x0012
Reg[0x1F] (RES1F) = 0x000
-------------------------------------------

---- EXTENDED PHY REGISTERS ----
RGMII_CTRL = 0x0000
RGMII_CTRL2   (0x33) = 0x0000
PHY_CONTROL       (0x10) = 0x5028
PHY_STATUS      (0x11) = 0xAF02
INTERRUPT_MASK      (0x12) = 0x0000
INTERRUPT_STATUS      (0x13) = 0x0000
PHY_ERR_COUNT       (0x15) = 0x0000
BIST_CONTROL       (0x16) = 0x0000
LEDCR       (0x18) = 0x6150
RGMIIDCTL   (0x0086) = 0x0077
IO_MUX_CFG  (0x0170) = 0x0C0F
--------------------------------
================================

[0]: Starting lwIP, local interface IP is 192.168.1.200
[LWIPIF_LWIP] NETIF INIT SUCCESS
Host MAC address-0 : 70:ff:76:1d:ec:f2
[LWIPIF_LWIP] Enet has been started successfully
[0]status_callback==UP, local interface IP is 192.168.1.200
UDP server listening on port 5001
[0] link_callback==UP
      8.575s : CPU load =   8.14 %
     13.575s : CPU load =   1.68 %
     18.575s : CPU load =   1.68 %
     23.575s : CPU load =   1.68 %
     28.575s : CPU load =   1.68 %

Kindly review and let us know your observations.

Thanks & Regards,
Chinchetti Abhishek

+1 Shaunak Deshpande 5 months ago in reply to Chinchetti Abhishek

TI__Mastermind 27122 points

Hi Abhishek,

I see there are differences between the registers point that there are issues with delays, both PHY status and control registers show difference in config.The issue is most likely due to incorrect RGMII delay configuration (clock/data skew) between MAC and PHY on the custom board.

DP83869 requires correct alignment between:

MAC internal delay
PHY internal delay (configured via RGMIICTL / RGMIIDCTL)

Recommended Debug Steps

1. Match EVM RGMII configuration

Program PHY registers on custom board to match EVM:
- RGMIICTL (0x32)
- RGMIIDCTL (0x86) = 0x0377

2. Check PHY strap status

Read STRAP_STS (0x6E) and verify:
- Operating mode = RGMII to Copper
- No unintended mode (e.g., bridge/SGMII)
- Delay mode straps match EVM

3. Validate MAC configuration: Ensure MAC (AM263x CPSW):

Is configured for correct RGMII mode (ID vs non-ID)
Speed/duplex matches PHY resolved values
Try forcing 100 Mbps to simplify timing

4. Scope RGMII signals

Probe at PHY pins:

TXC, TXD[0:3], TX_CTL
RXC, RXD[0:3], RX_CTL

Check:

Clock-to-data alignment (~1.5–2 ns skew expected depending on mode)
Clean transitions (no distortion)

5. Double-check hardware differences

Compare with EVM:

RGMII trace lengths (clock vs data skew)
Impedance control
Termination
Power rails and decoupling
Clock quality (jitter)

Based on the regs shared, i see:

- PHY is up and communicating correctly.
- Issue is not MDIO or basic PHY bring-up.
- Strong evidence points to RGMII timing/skew mismatch on the custom board.
- Start by aligning RGMII delay configuration with the TI EVM and validating timing on scope.

Regards,
Shaunak

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AM2634: AM2634 MAC TX Not Working & DP83869 PHY Loopback Failure (MDIO OK) And Not Pinging.