TCAN4550: SPI Transfer

Hello AP,

Please see the Software Optimization Tips section 5 of the TCAN45xx Software User's Guide (Link) for more detailed information on the use of the Length field during SPI transactions.

Each SPI read/write transaction must contain a 32-bit (or one word) SPI Header that contains the read/write op-code (0x41 or 0x61) the starting register or MRAM address, and the number of 32-bit words of data that will be read or written in the transaction or the "length" of the data portion of the SPI transaction.

The Length field can be set to 1 data word up to 255 data words allow bulk transfers of data into consecutive registers or MRAM blocks and improving the efficiency by eliminating the need to toggle the chip select between each register or MRAM block read/write transaction that also requires a new 32-bit header word.  This is sometimes called "Burst Reads and Writes."

However, there are some rules that need to be followed to avoid errors.  The device uses a FIFO on the SPI interface with the MCU to handle the frequency domain crossing between the SPI Clock used by the MCU and the high speed OSC clock used by the digital core.  The device has some monitoring and error checking features to ensure the SPI data passing through the FIFO is correct and doesn't contain errors.

• The Length field can't be zero and there must be at least one 32-bit data word for each read/write transaction.
• The number of data bits transferred must be in complete 32-bit words.  
• The number of data words transferred MUST match the value set in the Length field of the header.
• The SPI Chip Select Signal must toggle Low at the beginning of the SPI transaction, remain Low for the entire SPI transaction and toggle High at the end of the SPI transaction
• The SPI clock frequency needs to be at least 2MHz less than the OSC frequency to ensure the digital core has time to return the register or MRAM Read Data back into the FIFO before the MCU pulls it out using the SPI Clock on a SPI Read.

If any of these rules are violated there will be SPI errors due to an incorrect number of bits passing through the FIFO which will cause the relevant bits in the Status Register 0x000C to be set and the SPIERR flag in the Device Interrupt Register 0x0820 to be set which may cause the Interrupt pin (nINT) to pull Low.

If a SPI Error occurs on a Read, the data returned to the MCU may contain errors.  One possible reason for this would be that there was a noise glitch on the SPI clock that caused a false clock edge that resulted in an extra erroneous data sample resulting in an extra data bit.  This would be a violation of the data bits transferred didn't end on a valid 32-bit boundary.  

If an error occurs on a SPI Write, the device may discard the new incoming register or data value because it may be corrupted and the register write should be repeated to ensure the correct value is written to the register.

If the SPI transaction is terminated before the correct number of data words has been transferred (such as 10 instead of 24 as you have suggested), then this will result in a FIFO Underflow SPI Error.  The device does start writing to the MRAM block during these burst writes, and therefore the memory cells may be written with the new values.  If the chip select ended on an exact 32-bit word boundary, then it is possible the first 10 cells were written with the new values and a new SPI transaction with 14 words could be performed on the remaining 14 cells.  

However if a SPI Read or Write transaction results in one or more SPI Error bits being set, t is recommended to repeat the entire transaction with one that does result in one or more SPI error bits being set to ensure the data transferred is correct.

Regards,

Jonathan