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AM2434: Guidance Required on Shared GPMC Interface for NAND Flash and MSRAM

Kashish Thakur
Prodigy 10 points

Part Number: AM2434

Hello TI Experts,

I am designing a data acquisition device using AM2434 Sitara in which both NAND Flash (MT29F8G08ABACAWP-IT:C TR) and MSRAM (MR4A16B) are connected to the same GPMC controller, with shared GPMC control lines and 8-bit GPMC0AD/data lines. I have a few concerns regarding the robustness of this design and would appreciate your guidance:

  • The combined capacitive load of the connected memories on the shared GPMC lines is approximately 18 pF, while the GPMC pins support up to 20 pF according to the specifications. Is this margin sufficient for reliable operation, or are there additional signal integrity considerations I should verify?
  • Some boot mode pins are multiplexed with the GPMC data pins. After boot-up, can these shared pins cause any issue such as bus contention or data corruption during normal GPMC operation?
  • Since both memories share the same interface lines, are there any recommended hardware precautions or design guidelines to ensure stable communication?

Any suggestions or recommendations regarding this design would be very helpful. Thank you for your support.

  • 0
    TI__Intellectual 1420 points

    Hello Kashish Thakur,

    Anastas is out of office. He will reply early next week.

    Thank you for your patience!

    Best Regards,

    Borislav Lazarkov

  • 0 in reply to Borislav Lazarkov
    TI__Genius 12720 points

    Hello Kashish Thakur,

    Please allow me a bit more time. I am currently discussing that particular use-case with our Sitara GPMC hardware expert.

    I will let you know as soon as I have his feedback. Please expect that a certain delay in our response is possible (earliest tomorrow COB).

    Thanks !

    Best Regards

    Anastas Yordanov  

  • 0
    TI__Mastermind 30601 points

    Hi Kashish Thakur,

    The datasheet cap loading CL is what we used for timing analysis. Except for the 16-bit 133MHz synchronous mode, we actually ran timing analysis for GPMC from 3pF to 30pF  (the datasheet reads 5 to 20pF of loading).

    We recommend IBIS simulation to see if placement of the to GPMC memories might lead to unwanted signal reflections.

    The GPMC timings are configurable and may need extra time for the data bus AD[7:0] to settle before latching the data during writes and reads.

    More concerning are possible reflections affecting control signals like WE and OE. The memory state machines may not handle a non-monotonic signal edge. Signal reflections can distort the edge of the signal depending on layout. Therefore placement of the two memories may need to be very close to each other to minimize these reflections. For example one memory on the top side of the PCB and one on the bottom side with minimal trace from the via to each memory may minimize the reflection. Try it in an IBIS with HyperLynx Linesim for example.

    Signal buffers are an option to clean up signals, but the timing analysis needs to factor their propagation delay.

    The boot mode signals that are shared with GPMC pins should not cause contention if they are pulled with resistors to the logic level instead of shorted. The pull resistors may impact edge rate of the signals, and should be included with the IBIS sim. On the EVM we have a buffer that asserts boot mode pins during SOC reset and releases the boot mode after PORZ_OUT is driven high from the SOC, so the boot mode resistors are isolated. Refer to the EVM schematics.

    Hope this helps and apologies for the long delay.

    Regards,
    Mark