AM261-SOM-EVM: AM261x enet_lwip_cpsw example hangs after warm reset – works only after power cycle

Part Number: AM261-SOM-EVM
Other Parts Discussed in Thread: SYSCONFIG, DP83869

Hello TI Team,

I am working with AM261x and testing the enet_lwip_cpsw example from MCU+ SDK.

The application works correctly after power-on and Ethernet communication is successful. However, after resetting the board, the application no longer boots correctly and only prints a long hexadecimal dump on UART.

Example UART output:

000002010100000000000100414d323631580000000000000400cdab0000010001000000000000000000000000000000000000001aefc36abc625f8da980be8cd275a58eb77c6b83fc91c7548a793be4c020c2cded676ddf26b3db6361bf5fc01d7f3e71abc5cfc2b0ce553497c36284fa66dfbd00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f065c5297cfdc2c3882241850b4d3be1ba0804935a1a554ad09c09035621c40e6ba5c61056f45e282a50f115612f609b7858836916a1707f426f8aaed4068518CC

After this, the board hangs and the application does not execute.

The only way to recover is:

  • remove power completely
  • power ON again

Then the application works normally again.

I also noticed the SDK documentation states:

“If you need to reload and run again, a CPU power-cycle is MUST”

However, for a production device, the system must recover automatically after:

  • watchdog reset
  • warm reset
  • brownout/power fluctuation
  • software crash

without requiring a complete power removal.

I suspect:

  • CPSW/UDMA/PHY state is not getting reset properly during warm reset
    OR
  • external PHY / OSPI remains in stale state after reset.

I also checked the AM261x reset architecture documentation which shows separate PORz and warm reset paths.

Questions:

  1. Is this a known limitation of the enet_lwip_cpsw example only, or of the AM261x Ethernet subsystem itself?
  2. What is the recommended production-grade reset sequence for CPSW + lwIP?
  3. Is there an official Ethernet deinitialization/shutdown sequence before reset?
  4. Is external PHY reset mandatory during warm reset?
  5. Does TI recommend using POR reset instead of warm reset for Ethernet recovery?
  6. Is there any known issue related to OSPI reset during software reset on AM261x? I saw the datasheet mentions special handling for OSPI flash reset.
  7. Are there any reference examples showing successful repeated open/close/restart of CPSW/lwIP without requiring power cycle?

Environment:

  • Device: AM261x
  • SDK: MCU+ SDK (mcu_plus_sdk_am261x_26_00_00_01)
  • Example: enet_lwip_cpsw
  • Board Version: E2

Any guidance for implementing a robust production-grade recovery/reset architecture would be very helpful.

BR,
Akshay

  • Hi Akshay,

    The warm reset is not connected PHY Resets or the ethernet on-board connector logic, which are needed to re-init the example, but i do not expect "CCCC" prints to come. If you see these prints, it probably means that the OSPI Bootloader was not able to find a valid image and went into fallback UART Bootmode.

    As far as my local testing is concerned on TI AM26x EVMs, with OSPI boot mode and the binary flashed, the examples work fine after PORz but as expected, not after Warm reset (Resetn button on the launchpad).

    • Does TI recommend using POR reset instead of warm reset for Ethernet recovery?

    You need reset logic for PHYs, looking at the CPSW TRM, warm reset will reset the CPSW sub-system, but the external PHYs do not get reset.

    Regards,
    Shaunak

  • Hi Shaunak,

    I tried resetting the board using the PORz switch, but I am seeing the following UART output instead of the application booting:

    000002010100000000000100414d323631580000000000000400cdab0000010001000000000000000000000000000000000000001aefc36abc625f8da980be8cd275a58eb77c6b83fc91c7548a793be4c020c2cded676ddf26b3db6361bf5fc01d7f3e71abc5cfc2b0ce553497c36284fa66dfbd00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f065c5297cfdc2c3882241850b4d3be1ba0804935a1a554ad09c09035621c40e6ba5c61056f45e282a50f115612f609b7858836916a1707f426f8aaed4068518CC

    If you see these prints, it probably means that the OSPI Bootloader was not able to find a valid image and went into fallback UART Bootmode.

    Could you please suggest how to debug or resolve this issue?
    Should I verify the flashed OSPI image, boot mode switch settings, or SBL configuration again?

    Regards,
    Akshay

  • 1. Are you in OSPI bootmode?

    2. Are you using the right sbl_ospi_multicore elf file during flashing?

    Regards,
    Shaunak

  • Hi Shaunak,

    1. Yes, I am using the below switch configuration for OSPI boot mode. - 0 0 1 1

    2. I flashed the prebuilt SBL image sbl_ospi_multicore_elf.release.tiimage located at: 

    C:\ti\mcu_plus_sdk_am261x_26_00_00_01\tools\boot\sbl_prebuilt\am261x-lp
     

    However, I flashed the SBL only once initially. After that, I have only been re-flashing the application image since there were no changes in the SBL.

    Regards,
    Akshay

  • Hi Akshay,

    Just confirming once, the attached image is from DEV Bootmode. Also, please use this config:

    Regards,
    Shaunak

  • Hi Shaunak,

    Yes, I am configuring the switches as shown in the picture.

    BR,

    Akshay

  • Hi Akshay,

    Shaunak is currently OOO on business travel. Please expect a delay in response.

    Thanks,

    Ira

  • Hi Shaunak,

    I flashed the same example code on the Version A board (PROC193A), and surprisingly, it worked without any errors. What could be the issue with the Version E2 board (PROC193E2)?

    I made the following changes in the code and SysConfig to get it working on the Version A board:

    • Changed the PHY device from DP83826 -> DP83869
    • Changed the both PHY address.
    • Changed PHY pin mux from RMII to RGMII.

    Regards,
    Akshay

  • Hi Akshay,

    I did initially expect it to work, but in my case, my launchpad had some issues with the Warm Reset button. Other SDK examples do work after a warm reset.

    I am on travel right now and not having the hardware with me to test it, but my initial thought was the PHYs might be causing an issue by not re-setting. But thinking of it now, even if PHYs do not undergo reset, the enet application will still start, and incase PHYs give an issue, we should still see the code reach the PHY alive logic, in this case now, we see it works completely fine.

    The changes made are expected/ you can check the latest SDKs so you don't have to make these changes in the out-of-box examples, they support the REV-A by default. 

    Regards,
    Shaunak

  • Hi Shaunak,

    I just went through and compared the schematics of both Version A and Version E2 boards. I found a major difference between the two schematics.

    In Version A, there is a connection from the PORZ switch to the IO expander reset pin, but this connection is not present on the Version E2 board. Could this be the reason for the issue observed on the Version E2 board?

    Can I connect the PORZ switch connection to R191 and R364 to check this on the Version E2 board?

    Best Regards,

    Akshay

  • Hi Akshay,

    Let me loop in our hardware expert to comment on the schematics.

    Regards,
    Shaunak

  • Hi  , can you please help with the above hardware specific question on AM261x som evm.

    Regards,
    Shaunak