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DS250DF230: CDR not locking and raw bypass is not working

Luke Korte
Prodigy 200 points

Part Number: DS250DF230
Other Parts Discussed in Thread: DS280DF810

Hi

So a bit of background, I have a board that uses a DS280DF810 and a DS250DF230 which have 5 channels of 10GE ethernet. 
They both have the same electrical design, with some small changes, namely the DS250DF230 has external AC coupling caps. 
The DS280DF810 is working on all channels while I am struggling to get the CDR to lock on the DS250DF230.
Even more weird is that the DS250DF230 does not output anything even when I set the drivers to output raw data when the CDR is not locked. 
I have also checked that the diff signals are reaching the DS250DF230. I tried bypassing the chip with wire mods and removing the chip. This works and I can see the data come through.

Here is what I write to all the channels for the DS250DF230.
I am using the refclk_out from the DS280DF810 as the refclk_in (i.e. 25MHz).

    #modify_reg(address, data, mask)
    modify_reg(0xfc, 0x01, 0xff)
    modify_reg(0xff, 0x03, 0x0f)
    modify_reg(0x00, 0x04, 0x04)
    modify_reg(0x0a, 0x0c, 0x0c)
    
    #manually set data rate to 10.31250 Gbps with 25MHz clk
    modify_reg(0x60, 0x90, 0xff)
    modify_reg(0x61, 0xb3, 0xff)
    modify_reg(0x62, 0x90, 0xff)
    modify_reg(0x63, 0xb3, 0xff)
    modify_reg(0x64, 0xff, 0xff)
    modify_reg(0x09, 0x04, 0x04)
    modify_reg(0x18, 0x10, 0x70)
    modify_reg(0x2f, 0x00, 0x04)
    
    modify_reg(0x31, 0x20, 0x60)
    modify_reg(0x1e, 0x08, 0x08)
    modify_reg(0x1e, 0x00, 0xe0) #set output to raw when CDR is not locked
    modify_reg(0x3d, 0x80, 0x80)
    modify_reg(0x3d, 0x00, 0x40)
    modify_reg(0x3f, 0x40, 0x40)
    modify_reg(0x3e, 0x40, 0x40)
    modify_reg(0x3d, 0x0f, 0x1f)
    modify_reg(0x3f, 0x00, 0x0f)
    modify_reg(0x3e, 0x03, 0x0f)
    modify_reg(0x0a, 0x00, 0x0c)
    
    Some feedback from registers 
    read(0xef) 0e
    read(0xf0) 01
    read(0xf1) 15
    read(0xfe) 03
    
    read(0x01) for channel 0 = c0
    read(0x01) for channel 1 = 80
    
    I have confirmed that removing the ethernet signal clears bit 7 of 0x01.
    I am not sure the meaing of bit7.
    
    read(0x02) for channel 0 = 01
    read(0x02) for channel 1 = 01
    
    This tells me the data rate of the signal is below the min VCO. 
    But I am still confused that nothing is coming through with the raw data enabled. 
    
    My question is, what registers can I look at to try and diagnose the problem?
    Why is the raw data mode not working?
    Is it possible that I must use a 30.72MHz clock and use the default clock settings in reg 0x2f?
    
    Any suggestions would be much appreciated. 
    
    Thank you
    
    
    

  • 0
    TI__Expert 4442 points

    Hi Luke, 

    I will look into this. Please expect a response my Wednesday next week. 

    Best,

    Charles

  • 0 in reply to Charles Wang
    TI__Expert 4442 points

    Hi Luke,

    Please see my comments below: 

    • Can you read-back registers 0xA5 and 0x09 to confirm their current value. 
    • Check register 0x78 for CDR lock status.
    • For raw data output when CDR is not locked, Reg_0x09[5] must be set to 0. Please double check this bit.
    • Does asserting and release CDR reset (reg_0x0A bits 2,3) at the end of configuration sequence show different results? 
    • Read back registers 0x60-0x64 and 0x18 to confirm 25MHz ref-clk writes took affect

    Thanks,

    Charles

  • +1 in reply to Charles Wang
    Prodigy 200 points

    Hi Charles 

    Apologies, there were some incorrect pins routed to the chip, most importantly the clk_in.

    I was thrown off by the chip returning that it detected the 25MHz clock.

    All is working now as expected.

    Thank you anyway for your response, always appreciated.

    Regards