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DP83822IF: 100ms errors during ESD testing

Huang Feng
Prodigy 165 points

Part Number: DP83822IF

Hello,

During contact discharge testing (as part of the IEC 61000-4-2 ESD immunity test) on an SFP optical module paired with the DP83822IF PHY, I have intermittently observed bit errors lasting approximately 100 ms.

Software analysis:
When the PHY chip is reset, the CPU continues transmitting and receiving data. During this reset period, the received data does not match the transmitted data, and this mismatch is also counted as a bit error.

Investigation so far:
I found that the Deep Power Down function – a dedicated term from the DP83822IF datasheet – has a duration of exactly 100 ms. This suggests that the test interference may be triggering the Deep Power Down mode. However, after I adjusted the Deep Power Down Speed register to 50 ms and repeated the test, the bit error duration remained 100 ms.

Questions:

1. What other mechanisms of this PHY chip could cause this 100 ms bit error phenomenon during contact discharge ESD testing?

2. If the Deep Power Down function is indeed the root cause, is there a way to completely disable it?

Background context:
Our communication link includes filtering, so losing one or two packets during the test would not be a major issue. However, a continuous 100 ms data loss is considered a serious failure.

Thank you for your assistance.

  • 0
    TI__Mastermind 42245 points

    Hello,

    It is unclear what else on the device could be causing this communication error. Please note that most characterization efforts of this device were for linkup and not packet errors so support is limited. Is the ESD test being conducted on the SFP shield? Is it possible that the SFP is affected and not the PHY?

    If deep power down or any other similar state is triggered, there is need to manually revert the PHY back to operating state via SMI. Thus, I do not believe that this is the root cause. Is the PHY showing errors via 0x15?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 165 points

    Thank you for your support and guidance.

    We have another board that uses the same FPGA and the same SFP optical module. On that board, during contact discharge ESD testing, the maximum packet loss is only 1–2 packets.

    The new board, however, needs to support the 100BASE-FX protocol, so we added the DP83822IF PHY. Given the difference between the two boards, the issue most likely lies with this PHY.

    I noticed that the INT/PWDN pin can also trigger the Deep Power Down function . Does this also require a manual reset via SMI to recover?

    I have tried configuring this pin as an INT function, but the 100 ms bit error still occurs during testing. My current hypothesis is that ESD interference couples into this pin and directly triggers the Deep Power Down function. Is this a reasonable assumption?

    As a next step, we plan to read the RECR register (0x0015) to assist in further analysis, since our previous investigation focused only on PHY reset and did not consider other factors.

    Could you please provide any additional guidance or recommendations?

    Thank you.