DP83822IF: 100ms errors during ESD testing

Hello,

It is unclear what else on the device could be causing this communication error. Please note that most characterization efforts of this device were for linkup and not packet errors so support is limited. Is the ESD test being conducted on the SFP shield? Is it possible that the SFP is affected and not the PHY?

If deep power down or any other similar state is triggered, there is need to manually revert the PHY back to operating state via SMI. Thus, I do not believe that this is the root cause. Is the PHY showing errors via 0x15?

Sincerely,

Gerome

Thank you for your support and guidance.

We have another board that uses the same FPGA and the same SFP optical module. On that board, during contact discharge ESD testing, the maximum packet loss is only 1–2 packets.

The new board, however, needs to support the 100BASE-FX protocol, so we added the DP83822IF PHY. Given the difference between the two boards, the issue most likely lies with this PHY.

I noticed that the INT/PWDN pin can also trigger the Deep Power Down function . Does this also require a manual reset via SMI to recover?

I have tried configuring this pin as an INT function, but the 100 ms bit error still occurs during testing. My current hypothesis is that ESD interference couples into this pin and directly triggers the Deep Power Down function. Is this a reasonable assumption?

As a next step, we plan to read the RECR register (0x0015) to assist in further analysis, since our previous investigation focused only on PHY reset and did not consider other factors.

Could you please provide any additional guidance or recommendations?

Thank you.

Hello,

Can you please expand on PWDN pin triggering Deep Power Down function? My understanding is that this has to be set in registers before entering via pin. So if this is not set via registers, it is unlikely to be triggered.

This other board you mention, is it another instance of the same design with DP83822?

Can you again please clarify where the discharge spot is located? Is it on the SFP itself? Is it possible the SFP is disrupted and can act in different ways?

What level of ESD are you testing up to?

Sincerely,

Gerome

1. The INT/PWDN pin is a multiplexed function pin. According to the datasheet, the default value of the corresponding register configures this pin to the PWDN function.

The datasheet specifies a trigger pulse width of 10us for the RESET signal. However, for the PWDN function, the datasheet does not provide a required trigger pulse width. In our actual measurements, a pulse as short as a few tens of nanoseconds can trigger it – far smaller than the 10 µs reset pulse.

We have already tried reconfiguring the register to change the pin function from PWDN to INT. We also added filtering capacitors (100pF, 10nF, 47uF) to this pin. Nevertheless, the 100 ms data loss still occurs.

Therefore, we suspect that the ESD interference does not enter the chip primarily through this pin or its signal trace. Instead, it likely couples into the chip through other signal lines or the GND plane, and then falsely triggers the Deep Power Down function internally.

2. The other board uses the same FPGA and the same SFP optical module, but it does not include the DP83822IF PHY. That board experiences only 1–2 packet losses during the same ESD test. The new board adds the PHY to support 100BASE‑FX, so the difference strongly points to the PHY as the root cause. They are not two instances of the same DP83822 design.

3. The contact discharge point is located on the outer edge of the SFP metal cage, not on the SFP module itself. We cannot rule out SFP disruption entirely, but if the SFP alone were the issue, the board without the PHY would likely show similar packet loss – yet it only loses 1–2 packets. Hence, the PHY remains the primary suspect.

4. We are testing according to IEC 61000-4-2 Level 4 (8 kV) contact discharge.

Thank you.

Hello,

I understand how the behavior present may indicate deep power down is being entered. However, if the PHY were to enter power down or deep power down, the link would be severed. It should take longer for PHY to transition out of power down and subsequently re-establish link. A check for this would be to see if the link LED is being affected during the strike, as this would confirm this hypothesis. If link is stable through the strike, and only packet errors are present, I do not believe deep power down is being entered and exited.

Sincerely,

Gerome