DP83867IS: 10MBit packet loss with SGMII PHY TX

Do you know how we can figure out if we use an old or a new revision of the chip?

Hello Shane, Hello Heiko.

I have read the following marking from the affected component:

DP83867IS

TI24I

A9DL   G4

I assume A9 stands for September 2020. 

Is this a component where we need to set the bit, or is it a component where that shouldn’t be necessary anymore?

Best regards,

Bernd

Hi Bernd,

What value do you see in the PHY identifier registers?

Best,

Shane

Hello Shane,
I read the following values:

BCM.0> phy raw 0x21 0x002
0x02: 0x2000
BCM.0> phy raw 0x21 0x003
0x03: 0xa231

I assume, we have the chip revision 1(Bit 3:0 in PHY Identifier Register #2 (PHYIDR2), Address 0x0003). What does “chip revision 1” mean? Does the 10M_SGMII_RATE_ADAPT bit have to be set automatically for a 10 Mbit connection, or not?

Best regards,

Bernd

Hi Bernd,

I'm trying to get more background on this change, but right now all I can say is that its ok to set the 10M_SGMII_RATE_ADAPT bit when operating in 10M SGMII.

I'll try to provide an update this later this week. When I tested 10M SGMII on our DP83867-S-EVM I did not need to set this bit, so there looks to be a discrepancy between our tests. Do you see the SGMII autonegotiation complete at 10M in your system without setting this bit? My EVM showed the same register values as you described in 0x2 and 0x3 so perhaps this is not captured in the register.

I agree with your assumption that this is chip revision 1.

Best,

Shane

Hi Shane,
A customer reported issues with 10 Mbit. We were able to reproduce the issue. The data loss was 30%. I suspect that production purchased a large quantity of Phys at the start of the project, and this batch has not yet been used up. But that is just an assumption  on my part. It could therefore be that we still have Phys where the 10M_SGMII_RATE_ADAPT bit is not set automatically. We would therefore like to know which Phys we have.
We have now been running tests for several days with 100% 10Mbit traffic and have not detected any data loss. For this test, we manually set the 10M_SGMII_RATE_ADAPT bit to 0. When we set it to 1, we have a data loss of approx. 30%. So it is actually clear what we need to do to solve our problem. To be absolutely safe that this is the solution to our problem, we would like to know which chip version we have. The older one, where the 10M_SGMII_RATE_ADAPT bit has to be set manually, or the newer one, where the 10M_SGMII_RATE_ADAPT bit is set automatically.

We haven’t checked the SGMII autonegotiation because we believe it was successful. If it hadn’t been successful, no data could be transferred at all.

Thank you very much for your support and best regards,
Bernd

Hi Bernd,

Thank you for the context. I ran the top markings you provided and it looks like you've got the latest revision of DP83867. This being the case, I wouldn't expect setting the bit to be necessary.

The last time I tested 10M SGMII through our EVM I don't remember needing to set this bit. Let me put together another test setup and see if I can ping through these boards back to back again. I'll try to have this by tomorrow or Friday at the latest

Best,

Shane

Hi Bernd,

I ran a ping test through two of our DP83867-S-EVMs linked up at 10Mbps and did not run into issues. I did not have to set the SGMII_RATE_ADAPT bit in my test. There seems to be some difference between your device or board and my setup that's causing this.

Does this same behavior show on all of your boards, or if not, what amount of boards do show this behavior?

Do you have DP83867-S-EVMs to test with? You can try taking the PHY from your board and place it onto a DP83867-S-EVM. Then use a back-to-back SGMII connection with another DP83867-S-EVM to ping through both boards while linked up at 10Mbps. This would model my setup in the image shown and will tell us whether the need for SGMII_RATE_ADAPT is tied to the PHY IC or to the board/MAC.

EVMs are available on TI.com, or if your company has a local assigned TI engineer they can help you to source these as well. To get register access we typically use the MSP430 launchpad with USB2MDIO software, however any MDIO controller should be able to do this when attached to the MDIO/MDC lines of the EVM.

Best,

Shane

Hello Shane.

Thank you very much for the detailed tests you carried out to help us. I can see a significant difference between your test setup and our switch design. You have connected two DP83867-S EVMs directly to each other via SGMII. In our setup, the DP83867IS is connected to a Broadcom switch via the SGMII interface. Unfortunately, I don’t know what happens in the PHY when the 10M_SGMII_RATE_ADAPT bit is set to 0. However, this is obviously important for the Broadcom switch. When the bit is set to 1, I measure the following eye diagram:

If we set the Bit to 0 we measure the following eye:

We have been running tests involving power-up/power-down cycles for several days now. So far, we have not detected any packet loss. We therefore now assume that we need to set the SGMII_RATE_ADAPT bit to 0 via software for 10 Mbit.
Kind regards,
Bernd Zehren

Hello again.
Please ignore the eye diagram measurements above. They have nothing to do with the 1 Mbit problem. They were taken in a different context.
Best regards,
Bernd