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DP83822H: Power-Up Sequences and CL for external crystal

Takashi Imai
Intellectual 300 points

Part Number: DP83822H
Other Parts Discussed in Thread: DP83TC811EVM, DP83TC811, DP83822EVM

Hello,

Please let me confirm the DP83822H power-up sequence and the recommended CL value when using Crystal.

1.About Power-Up Sequences

There is a description of "AVD (analog supply) ramp delay post VDDIO (digital supply) ramp. AVD and VDDIO potential must not exceed 0.3 V prior to supply ramp." in the table of 7.6 Timing Requirements, Power-Up Timing in the data sheet of DP83822H, and there is "(3) AVD ramping up after VDDIO ramp completion is preferred to avoid false detection of lower level of VDDIO in any corner case" in the annotation.  There are questions from a customer about this content. Please answer the following four questions.

1)Can we understand the meaning of these words as "Either AVD or VDDIO can be activated first, but after one of them is activated, the other must be activated within 100 ms. However, it is preferable to start the AVD after the VDDIO is started to avoid low-level false positives of the VDDIO."?

2)From the content of the comment (3), it is understood that it is preferable to launch AVD within 100 ms after VDDIO is launched, but what are the consequences and concerns if this is not observed?

3)Looking at the circuit diagram of DP83TC811EVM on the evaluation board, it seems that the rising order and timing of VDDIO and AVD are not taken care of. Is there any problem?

4)For the circuit under design, I am thinking of starting up VDDIO and AVD at the same time as the evaluation board in order to reduce cost, but is it necessary to follow the comment (3)? Is it all right if we start up at the same time?

2.Crystal Terms of Use

 
 

The recommended capacity of the CL for use with the DP83822H crystal oscillator is 20 pF as shown in the data sheet below.


On the other hand, as shown in the red box below, the evaluation board uses a crystal oscillator with a CL of 12 pF and a combined capacitance of 12 pF.

In the circuit currently being designed, the CL is designed at 12 pF like the evaluation board. Is there any problem?

Thank you,

T.Imai

  • 0
    TI__Genius 13350 points

    Hi Imai-san,

    I will review this questions and will get back to you this week.

    Best regards,

    Greg

  • 0 in reply to Gregory Kobyakov
    Intellectual 300 points

    Hi Greg-san,

    Thank you for your support. I am looking forwad to having your reply in this week.

    Best regards,

    T.Imai

  • 0 in reply to Takashi Imai
    TI__Genius 13350 points

    Hi Imai-san, 

    Thank you for your patience. I am checking internally and will provide an answer tomorrow.

    Best regards,

    Greg

  • 0 in reply to Gregory Kobyakov
    TI__Genius 13350 points

    Hi Imai-san,

    Did you mean to say 22pF capacitance instead of 12pF? In the EVM schematic that you shared it looks like the crystal has a 22pF load capacitor. Is that the one the customer is using?

    Best regards,

    Greg

  • 0 in reply to Gregory Kobyakov
    Intellectual 300 points

    Hi Gregory-san,

    Thank you for your reply. My meaning is that EVM is using 12pF, the datasheet recommendation is 20pF, so the customer wants to use 12pF.

    Is it OK to use 12 pF instead of datasheet's recommended value of 20pF? Please reply to this questios.

    Also please reply to the following customer's questions about About Power-Up Sequences.

    1)Can we understand the meaning of these words as "Either AVD or VDDIO can be activated first, but after one of them is activated, the other must be activated within 100 ms. However, it is preferable to start the AVD after the VDDIO is started to avoid low-level false positives of the VDDIO."?

    2)From the content of the comment (3), it is understood that it is preferable to launch AVD within 100 ms after VDDIO is launched, but what are the consequences and concerns if this is not observed?

    3)Looking at the circuit diagram of DP83TC811EVM on the evaluation board, it seems that the rising order and timing of VDDIO and AVD are not taken care of. Is there any problem?

    4)For the circuit under design, I am thinking of starting up VDDIO and AVD at the same time as the evaluation board in order to reduce cost, but is it necessary to follow the comment (3)? Is it all right if we start up at the same time?

    It will be about a week since sustomer's questions, so there is an urgent response request from the customer. Please answer all questions by the end of the day, so that I can reply to the customer on 19. May.

    Thanks & Regards,

    T.Imai

  • 0 in reply to Takashi Imai
    Intellectual 300 points

    Hi Gregory-san,

    I understand your meaning.  I will conform to the customer whether 12pF is typo and they are thinking to use 22pF as same as EVM, and get back to you.

    It is appreciated if you repy to the about Power-Up Sequences.

    Best Regards,

    T.Imai

  • 0 in reply to Takashi Imai
    Intellectual 300 points

    Hi Gregory-san,

    I confirmed about capacitance. Customer's 12pF meant the load capacity of the crystal: 22 pF// 22 pF=12 pF (E12 series). As a single part's capacitance is 22 pF. 

    So, the customer's questions are,

    1) although the datasheet is 20 pF, is there any problem if we use 2 pieces of 22 pF which is the same as EVM?

    2) Just for reference, is there no problem to use 2 pieces of 27pF (27pF // 27pF)? 

    And, I'm sorry to bother you, but I'd like you to answer about the Power-Up Sequences by the end of today. The customer planned to fix their circuit with the TI products on 18, May if there was no problem from TI. If you answer today, they can fix components with TI products tomorrow 19,May Japan time.

    Best Regards,

    T.Imai

  • 0 in reply to Takashi Imai
    TI__Genius 13350 points

    Hi Imai-san,

    I checked with my team, this load capacity is fine as long as it is verified with the crystal manufacturer that the customer is using. There is no problem using 2 capacitors in parallel. 

    Regarding your questions about Power-Up Sequences:

    • Where is this excerpt from? I did not see it in our datasheet.
    Takashi Imai said:
    Either AVD or VDDIO can be activated first, but after one of them is activated, the other must be activated within 100 ms. However, it is preferable to start the AVD after the VDDIO is started to avoid low-level false positives of the VDDIO

               It is saying that while either the VDDIO (I/O supply) or AVD (analog supply) can be powered first, it is recommended to power VDDIO first. The second supply powered should also be powered within 100ms of the first. Powering VDDIO first is done to avoid false detection of lower level of VDDIO. Although it is recommended to power VDDIO first, it is OK to power AVD and VDDIO at the same time. I also assume you meant the DP83822EVM and not the DP83TC811 EVM! Let me know if that was intentional.

    Best regards,

    Greg

  • 0 in reply to Gregory Kobyakov
    Intellectual 300 points

    Hi Gregory-san,

    Thank you for your reply.

    About the load capacitance of the chrystal, I understood that the custome can use both  22pF and 27pF capacitors in parallel as long as it is verified with the crystal manufacturer that the customer is using.   Please correct me if this understanding is wrong.

    The customer also plans to use the DP83TC811 with their system. There is the same question. If the customer check with the crystal manufacturer they are using, is there no problem as an IC to use both capacitors of 22 pF and 27 pF in parallel as a load capacity of crystal?

    About Power-Up Sequences:

    Regarding your question below,  

    > Where is this excerpt from? I did not see it in our datasheet.

    >      Takashi Imai said:
    >          Either AVD or VDDIO can be activated first, but after one of them is activated, the other must be activated within 100 ms. However, it is preferable to
    >          start the AVD after the VDDIO is started to avoid low-level false positives of the VDDIO

    that is how the customer understood the following excerpt from the datasheet. However I understand your reply, and would like to inform what you repled.

    The DP83TC811 EVM was intentional. The customer asked whether the power up sequence method of DP83TC811 is the same as the DP83822. This is because the DP83TC811 does not have power up/down sequence information in the datasheet.

    So, please reply about two below.

    • Is DP83TC811 power up sequence he same as DP83822?
    • If the customer check with the crystal manufacturer they are using, is there no problem as the DP83TC811 to use both capacitors of 22 pF and 27 pF in parallel as a load capacity of crystal?

    Best Regards,

    T.Imai

  • 0 in reply to Takashi Imai
    TI__Genius 13350 points

    Hi Imai-san,

    Takashi Imai said:
    About the load capacitance of the chrystal, I understood that the custome can use both  22pF and 27pF capacitors in parallel as long as it is verified with the crystal manufacturer that the customer is using.   Please correct me if this understanding is wrong.

    Yes, your understanding here is correct. 

    Takashi Imai said:
    Is DP83TC811 power up sequence he same as DP83822?

    I do not currently support the single-pair Ethernet PHYs, like the DP83TC811, so I will have to check internally with the team about this. 

    Best regards,

    Greg