• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 90 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM8330: PIN CONFIGURATION during rest

Koki Tsushima
Intellectual 975 points

Part Number: LM8330

Hi experts,

 

What is PIN CONFIGURATION during rest? Page 7 just shows PIN CONFIGURATION after Rest, but I need same data when reset. I want to know expecially for KPXn / KPYn / IREQN / SCL,SDA.

Best 

Koki

  • +1
    TI__Guru 61408 points

    Hi Koki,

    By "rest" I assume you are talking about RESET. 

    The exact state of the I/O's for this device is not defined when nRESET = LOW. I assume however that the I/O's will be in a floating / high-z state, but will not be active as outputs or inputs until the nRESET pin passes the power-on reset threshold. 

    i.e. when nRESET is held LOW, the I/O's will no longer be outputting any logic, the I/O's will not register input reads, etc. 

    The state described on page 7 is referring to when the device is passed a power-on reset threshold. This is not talking about when nRESET is held LOW. 

    Regards,

    Tyler