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AM62A3: AM62A34ASMSIANFRQ1 DDR4 clk RE issue

wang dong
Prodigy 40 points

Part Number: AM62A3

hi expert 

we are using AM62A34ASMSIANFRQ1 , the DDR4 clk is set as 800MHZ ,and we find that the harmonic frequece 1.6G is above the limit during EMC RE test . 

we had enable DBI . and we find the PLL support SCG , can we set SCG enable? how to set it ? 

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  • 0
    TI__Guru* 94741 points

    Spread spectrum is not supported for DDR PLL.  You can possibly mitigate the harmonics by slightly changing the DDR frequency to 790MHz for example.

    BTW, speed grade of the AM62A you are using is capable of max DDR frequency of 1600MHz.  So you could run at 1580Mhz for example.  Use the DDR Register Configuration Tool to change the DDR configuration for the new frequency: dev.ti.com/.../

    Regards,

    James 

  • 0 in reply to JJD
    TI__Mastermind 19801 points

    Dear Dong.

    would you please check the post from James and let us know your feedback?

    JJD said:

    Spread spectrum is not supported for DDR PLL.  You can possibly mitigate the harmonics by slightly changing the DDR frequency to 790MHz for example.

    BTW, speed grade of the AM62A you are using is capable of max DDR frequency of 1600MHz.  So you could run at 1580Mhz for example.  Use the DDR Register Configuration Tool to change the DDR configuration for the new frequency: dev.ti.com/.../

    thanks a lot!

    yong

  • 0 in reply to JJD
    Prodigy 40 points

    hi JJD ，Yong

    thank you for your quick feedback .  the DDR is running at 1600MHZ in my board ,not 800MHZ

    Finally , we plan to optimize the layout instead of changing DDR clock . 

    thank you . 

  • 0 in reply to wang dong
    TI__Mastermind 19801 points

    Dear Dong.

    okay, let us close this ticket.

    Please submit new ticket if you need support later.

    thanks a lot!

    yong