Part Number: DP83TC812S-Q1
Hello!
snla389f describes the sequence of register writes for initialization and TDR runs. Many of the registers/bits listed in these procedures are undocumented in the datasheet. Is there any documentation on what these bits are?
For context, we are having no issues using the sequence (the PHY basically works as expected), and understand that the startup registers are for OPEN Alliance compatibility.
Things seem to be working regardless, so it's not a huge issue if these are simply “bits you must set for compatibility/to run TDR”, but any extra details we can get would be appreciated to advise our own documentation/analysis.