TMDS181: TMDS181 - Request for Exact Register Sequences for Clock Counter (EyeScan Equivalent), Adaptive EQ Halt, and Fixed EQ Fallback

Hi,

Please see my response below. What is the specific inter-op issue you are having?

1. TMDS Clock Counter Registers & Frequency Conversion Formula (EyeScan Equivalent)

• We need to measure the actual frequency of the incoming TMDS clock to choose the correct fallback path (separating 1080p60 at ~148.5MHz from 4K60Hz at 297MHz/594MHz).

• Please provide the exact internal clock counter register addresses and the mathematical conversion formula/equation to calculate the actual TMDS Clock frequency (in MHz) from those raw values, exactly as counted and displayed in the TI EyeScan control software.

You can read out the TMDS181 register for the estimated clock frequency.

For Clock_Detect

This is detected using Page 1 Register 0xB1 Bit 7

For Clock Rate

This is detected using Page 1 Register 0xB0 Bit [7:4]

To calculate the actual frequency = (Hex value of [7:4] -> Convert to decimal) * 25 + 25. Please note this is a rough estimate of the actual clock frequency.

To access page 1 registers, write 0x01 to register 0xFF. 

To go ack to page 0 registers, write 0x00 to register 0xFF.

2. Status Monitoring Registers for Adaptive EQ and Link Lock Failure

• Which specific status registers and bit combinations should the firmware poll to reliably distinguish a failed/abnormal link state from a stable one within the 150ms window? We need the exact bits that indicate signal detection is active, but adaptive EQ or the CDR/Channel lock has failed to stabilize.

You can read Page 1 register 0x00. If Page 1 register 0x00 returns a value of 0xC3, this means TMDS181 is in retimer mode.

3. Precise Sequence to Halt/Freeze the Ongoing Adaptive EQ Loop

• When Adaptive EQ fails to converge, we must immediately halt the automatic routine before applying manual parameters.

• What is the exact step-by-step I2C sequence to completely freeze and terminate the internal automatic adaptive equalization state machine?

To stopped the adaptive EQ, this can be done using Page 0 register 0x0Ah bit 5 as shown below. Set bit 5 to 0 will change the EQ from adaptive to fixed.

4. Transition Sequence to Fixed EQ Mode (7.5dB Mid-range)

• After freezing the adaptive loop, we need to force Fixed EQ mode with a 7.5dB setting.

• Please provide the precise register address and safe bitmask to force Fixed EQ and select the Mid-range value without corrupting critical default bits.

• Which specific register bit must be toggled immediately afterward to initiate an instantaneous CDR re-lock based on the newly applied manual fixed EQ values?

Please see my response in question #3. For fixed EQ, please see the table below. Once the fixed EQ has been set, the APPLY_RXTX_CHANGES bit (Register 0x0A, bit 4) needs to be set.

Thanks

David

Hi,

Please see my response below. What is the specific inter-op issue you are having?

1. TMDS Clock Counter Registers & Frequency Conversion Formula (EyeScan Equivalent)

• We need to measure the actual frequency of the incoming TMDS clock to choose the correct fallback path (separating 1080p60 at ~148.5MHz from 4K60Hz at 297MHz/594MHz).

• Please provide the exact internal clock counter register addresses and the mathematical conversion formula/equation to calculate the actual TMDS Clock frequency (in MHz) from those raw values, exactly as counted and displayed in the TI EyeScan control software.

You can read out the TMDS181 register for the estimated clock frequency.

For Clock_Detect

This is detected using Page 1 Register 0xB1 Bit 7

For Clock Rate

This is detected using Page 1 Register 0xB0 Bit [7:4]

To calculate the actual frequency = (Hex value of [7:4] -> Convert to decimal) * 25 + 25. Please note this is a rough estimate of the actual clock frequency.

To access page 1 registers, write 0x01 to register 0xFF. 

To go ack to page 0 registers, write 0x00 to register 0xFF.

2. Status Monitoring Registers for Adaptive EQ and Link Lock Failure

• Which specific status registers and bit combinations should the firmware poll to reliably distinguish a failed/abnormal link state from a stable one within the 150ms window? We need the exact bits that indicate signal detection is active, but adaptive EQ or the CDR/Channel lock has failed to stabilize.

You can read Page 1 register 0x00. If Page 1 register 0x00 returns a value of 0xC3, this means TMDS181 is in retimer mode.

3. Precise Sequence to Halt/Freeze the Ongoing Adaptive EQ Loop

• When Adaptive EQ fails to converge, we must immediately halt the automatic routine before applying manual parameters.

• What is the exact step-by-step I2C sequence to completely freeze and terminate the internal automatic adaptive equalization state machine?

To stopped the adaptive EQ, this can be done using Page 0 register 0x0Ah bit 5 as shown below. Set bit 5 to 0 will change the EQ from adaptive to fixed.

4. Transition Sequence to Fixed EQ Mode (7.5dB Mid-range)

• After freezing the adaptive loop, we need to force Fixed EQ mode with a 7.5dB setting.

• Please provide the precise register address and safe bitmask to force Fixed EQ and select the Mid-range value without corrupting critical default bits.

• Which specific register bit must be toggled immediately afterward to initiate an instantaneous CDR re-lock based on the newly applied manual fixed EQ values?

Please see my response in question #3. For fixed EQ, please see the table below. Once the fixed EQ has been set, the APPLY_RXTX_CHANGES bit (Register 0x0A, bit 4) needs to be set.

Thanks

David

Hello David! Is it possible to get a full description of the Page 1 registers? The datasheet available on the website - https://www.ti.com/lit/gpn/tmds181 - doesn't contain a description of the registers you referenced in your answer above.

Thank you in advance for your support.

Hi,

Page 1 registers are for TI internal debugging only, unfortunately I can't share the full document, but I will be happy to answer any additional questions you may have.

Thanks

David