TUSB7320: TUSB7320 questions

Motoyasu Hattori said:

*1
When they do not use the following pins, which is treatment, pull-up, pull-down or floating?
USB_SSRXP_DN2,  USB_SSRXN_DN2,  USB_DM_DN2  USB_DP_DN2

these pins can be floating.

Motoyasu Hattori said:

hich frequency (24MHz or 48MHz) of OSC/Crystal does TUSB7320 use as default?
Also, could you please let us know the pin/register setting related with clock frequency?

48Mhz crystal should be used.

Motoyasu Hattori said:

Which type of PWRON# configuration, "Open Drain" or "Push-pull" pin?
I seem Pull-pull pin, but please advise us.

PWRON# is push pull pin.

Motoyasu Hattori said:

What is purpose of SMI pin?

SMI  used  by BIOS software to enable System Management Interrupts

Motoyasu Hattori said:

*6.
What is purpose of JTAG pins?

JTAG pins are J-Tag interface for ATE testing for boundary scan.

I will give more details about GRST later.

Best

Brian

Brian-san,

Thank you for your support.  I have the additonal questions.  Could you please answer the following?

*3
Could you please let us know the sequence limitation of both GRST# and PERST#?
My customer wants the following. Could you please let us know any issues?
    De-Assert (Low->High) : GRST# -> PRST#
    Assert (High->Low) : PRST# -> GRST#

*7
We can see the power-down sequence on the datasheet 7.3.1.2.

>7.3.1.2 Power-Down Sequence
>1. Assert PERST# to the device.
>2. Remove the reference clock.
>3. Remove the 3.3-V and 1.1-V voltages

Is it OK for TPS7320 to do PETST#, reference clock and power on the same timing? If you have any time requirement on each lines, please advise us. (For example, PERST# assert timing is required PCIE_REFCLK, but VDDA/VDD33 and VDD11 power-down is same time. etc.)

*8
Datasheet writes PD/PU status on each pins. Could you please let us know "internal PD register value" and "internal PU register value" on each pins?

Thanks and best regards,
M.Hattori.

Motoyasu Hattori said:

Could you please let us know the sequence limitation of both GRST# and PERST#?
My customer wants the following. Could you please let us know any issues?
    De-Assert (Low->High) : GRST# -> PRST#
    Assert (High->Low) : PRST# -> GRST#

GRST# should be low at  least 3 ms after both 3.3v and 1.1v are stable.

PERST should be low at least 100 ms after both 3.3v and 1.1v are stable.

PERST should be low at least 100 us after both PCI_CLK is stable

Motoyasu Hattori said:

Datasheet writes PD/PU status on each pins. Could you please let us know "internal PD register value" and "internal PU register value" on each pins?

around 22k for internal PU/PD resistor

Motoyasu Hattori said:

Is it OK for TPS7320 to do PETST#, reference clock and power on the same timing? If you have any time requirement on each lines, please advise us. (For example, PERST# assert timing is required PCIE_REFCLK, but VDDA/VDD33 and VDD11 power-down is same time. etc.)

You do need to assert PERST first but no timing requirement.

Best

Brian

Brian-san,

Thank you for your support.  But I have one addional question.  Could you please let us know the status of each pins on GRST# condition?

Thanks and best regards,
M.Hattori.

Hi M.Hattori.:

     Do you use J-tag or GPIO pins? if not , just leave it unconnected.

Best

Brian

Hi M.Hattori.:

     If you don't use Jtage, just pulldown on Jtag_RST pin and leave all other Jtag pins floating.

   If you use J-tage, You need to pullup all jtag pins ( except Jtag-TDO)

Best

Brian