Part Number: TLK10232EVM
Other Parts Discussed in Thread: TLK10232, TEST2
RE_ TI Support for HP Israel.msg
We are seeking your support with an unresolved issue using the TLK10232.
Summary:
- Setup: TLK10232 EVM connected to our FPGA-based tester board via optical link
- Test1 (EVM loopback) – PASS
- Test2 (EVM + system traffic) – PASS
- Test3 (IBERT / PRBS on both sides) – FAIL (no synchronization)
Details:
- PRBS31 generated and verified on both sides
- AN and LT disabled
- SYNC_STATUS_CHECK_DISABLE set
- Multiple TX/RX equalization settings tested (no impact)
- Configuration script attached (same used for working tests)
Observation:
When connecting the EVM to our system for IBERT, there is no sync/lock indication, although both sides work independently.
When connecting the EVM to our system for IBERT, there is no sync/lock indication, although both sides work independently.
We would appreciate your guidance on:
- Required configuration for IBERT interoperability between EVM and external FPGA
- Any known limitations or required alignment (clocking, polarity, training, etc.)
- Review of our configuration for potential mismatches
This issue is currently blocking our progress.
See attached correspondace.
