SN65DSI83-Q1: Regarding the REFCLK

Hello,

If the REFCLK is used as the LVDS source, it should be connected to an oscillator, not a crystal.

The frequency of the REFCLK will depend on the LVDS clock frequency. The LVDS clock frequency, which is based on the display's pixel clock rate, should be a multiple of the REFCLK frequency.

For example, if the LVDS clock frequency required used is 75 MHz, then a REFCLK at 25 MHz could be used with setting the REFCLK_MULTIPLIER field to multiply by 3.

It is acceptable to use 25 MHz REFCLK if the clock jitter specifications and other specs mentioned in the datasheet are met.

Alternatively, the DSI clock could also be used as the LVDS clock source.

Best regards,
Ikram

Hello,

Thank you for your response.

You are right — the device connected to `REFCLK` should be an oscillator, not a crystal.
Is the lower limit of 25 MHz based on the oscillator’s tolerance included in the specification? If a 25 MHz typical oscillator is used, would any issues arise if the actual frequency drops below 25 MHz due to tolerance?

Hello,

Since the device specifications are only validated for 25 MHz REFCLK, it's a datasheet requirement that the oscillator used should not go below that limit. 25 MHz as the minimum lower limit, is included in the spec, however, lower than that is not within the specification.

What is the LVDS and pixel clock rate used for your display?

Best regards,
Ikram

Hello,

Thank you for your response.

I will answer the question.

• Pixel clock: 23–27 MHz, typ. 25 MHz
• LVDS lane rate: 161–189 Mbps/lane, typ. 175 Mbps/lane

Hello,

In that case, it should be okay to use 25 MHz REFCLK, but they could also use higher up to 27 MHz, this is up to your discretion as long as the datasheet REFCLK specs are met.

Best regards,
Ikram

Hello,

Based on the LCD specifications, it is acceptable to use 25 MHz since the required range is 23–25 MHz. However, SN65DSI83-Q1 cannot be used below 25 MHz, so I understand that the selection should be made with that constraint in mind.

Thank you very much.

Hello,

T.T said:

• Pixel clock: 23–27 MHz, typ. 25 MHz
• LVDS lane rate: 161–189 Mbps/lane, typ. 175 Mbps/lane

Since you mentioned earlier that the pixel clock rate is 23 - 27 MHz, please check whether it can support 23 - 25 MHz only, or 23 - 27 MHz.


LVDS clock source alternative: DSI clock

Additionally, I wanted to mention that other than the external REFCLK, you can also use the DSI clock lane as LVDS clock source.

This could be a potential alternative instead of external REFCLK, as long as the DSI clock rate is within the datasheet specifications as well. This is set by having HS_CLK_SRC = 1 for MIPI D-PHY clock, HS continuous mode

The DSI clock input frequency must be between 40 - 500 MHz, and the DSI_CLK_DIVIDER field is used to divide the DSI clock rate to get the pixel clock or LVDS clock rate.

For example, with a 150 MHz DSI clock, the divider can be set to 6 to output 150/6 = 25 MHz LVDS clock rate.

Best regards,
Ikram