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SN65DSI83-Q1: Regarding the REFCLK

T.T
Prodigy 20 points

Part Number: SN65DSI83-Q1

Hi Team, 

Since the LCD-side frequency range is 23–27 MHz (typ. 25 MHz), we are planning to use the LVDS pixel clock at the lower limit of 25 MHz.
We intend to connect a 25 MHz external crystal to `REFCLK`.

I have two questions:
- Is it acceptable to operate at the lower limit? If there are any possible risks, please let me know.
- If the crystal frequency reaches 25 MHz due to temperature effects or other factors, what impact would that have on operation? Also, would it be better to connect `REFCLK` to `GND` instead?

 

  • 0
    TI__Mastermind 29150 points

    Hello,

    If the REFCLK is used as the LVDS source, it should be connected to an oscillator, not a crystal.

    The frequency of the REFCLK will depend on the LVDS clock frequency. The LVDS clock frequency, which is based on the display's pixel clock rate, should be a multiple of the REFCLK frequency.

    For example, if the LVDS clock frequency required used is 75 MHz, then a REFCLK at 25 MHz could be used with setting the REFCLK_MULTIPLIER field to multiply by 3.

    It is acceptable to use 25 MHz REFCLK if the clock jitter specifications and other specs mentioned in the datasheet are met.

    Alternatively, the DSI clock could also be used as the LVDS clock source.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 20 points 
    Hello,

    Thank you for your response.

You are right — the device connected to `REFCLK` should be an oscillator, not a crystal.
Is the lower limit of 25 MHz based on the oscillator’s tolerance included in the specification? If a 25 MHz typical oscillator is used, would any issues arise if the actual frequency drops below 25 MHz due to tolerance?